Arm pl330 DMA controller development (1)

I. Introduction to DMA

As a technology used to transmit data between CPUs and peripherals, DMA is widely used in various computer architectures. Its biggest advantage is that it can transmit data from memory to peripherals without CPU interference. This article describes how to operate the DMA controller in s5pc100. ExamplesCodeAll are verified on the fs_s5pc100 platform. On the far-sighted fs_s5pc100 platform of Huaqing, The pl330 DMA controller enables multiple DMA transmission modes, including memory to memory, memory to serial port, and serial port to serial port.
First, we will briefly introduce what DMAc is. DMAc is an adaptive controller of the advanced microcontroller bus system. It is designed by arm and based on primecell technical standards, DMAc provides an Axi interface to execute DMA transmission and two APB interfaces to control this operation. DMAc uses an APB interface to execute trustzone Technology in secure mode, other operations are performed in non-secure mode. DMAc includes a small instruction set to provide flexible and convenient operations. To reduce memory requirements, DMAc uses variable-length commands.
Unlike arm11 and earlier series chips, s5pc100 uses the pl330 (DMA controller core) based on the primecell technology standard. From the programming perspective, it provides flexible instruction sets, allowing you to use more combinations to operate DMA. In terms of hardware, it enables multi-thread management on hardware, you can write the code at a time to complete the required work normally. Therefore, it is difficult to develop the DMA.
Ii. Brief description of pl330

DMAc contains a module that executes commands and controls data transmission. DMAc uses the Axi interface to access the commands stored in the memory, DMAc can also store some temporary commands in the cache. We can configure the row width and depth.
Of course, the eight channels of DMAc are configurable, and each can support the operation of a single concurrent thread. In addition, there is also a management thread dedicated to initializing the DMA channel. It is used to ensure that every thread is working normally, and it uses round-robin to handle it when it chooses to execute the next active DMA channel.
DMAc uses a variable-length instruction set in the range of 1 to 6 bytes, and provides a separate PC register for each channel. When a thread needs to execute an instruction, search from the cache first. If a match is found, the data is immediately supplied. If the thread is stopped, DMAc uses the Axi interface to perform a cache line filling operation.
When a DMA channel thread executes the load/store command once, DMAc adds the command to the related read queue and write queue. DMAc uses the queue as a command storage zone, it is used to preferentially execute the commands stored in it. DMAc also contains an mfifo data cache, which is used to store read/write data during DMA transmission.

DMAc also provides multiple interrupt outputs. without interference from the microprocessor, the peripheral request interface also provides the ability to transmit memory to peripherals and from peripherals to memory, the dual-Apb interface supports both secure and non-secure modes. During programming, you can use the APB interface to access status registers and directly execute DMAc commands.

 
Figure 1 DMA module diagram in s5pc100