Arm Seven exception source and exception processing flow (four steps and three steps)

Arm Seven exception sources and exception handling processes

2014-11-30 Haidian District, Beijing Zhang Junhao

arm Seven kinds of anomaly sources and their working modes                   &N Bsp                          ,         &NB Sp                          ,         &NB SP;
exception SOURCE                                   nbsp	meaning
RE set  (reset)	Reset exception source	SVC Mode (Supervisor protected mode)
Sw I (software interrupt )	soft interrupt exception source	svc mode                       &NBS P
Un Define (undefined instruction)	undefined directive exception source	und mode                       &NBS P
Pr Efetch abort                            /		abort mode                                    
Da Ta abort                               &NB Sp	data anomaly source	abort mode                                    
IR q  (interrupt request )	External exception source	IRQ mode                       &NBS P
FIQ (Fast Interrupt Request)	Fast Interrupt Exception Source	Fiq mode

The entry process for ARM exception handling (processor handling of specific exception events) (Hardware AutoComplete):

Four Step ( Two backup two modifications) Three small steps:

(1) Copy CPSR (Current program status register )To Spsr_<mode> (Save current program status register Saved ）
(2) Set the appropriate CPSR bit:
To change the processor state into the ARM state (exception handling cannot be returned in thumb)
2--changing the processor mode into the appropriate exception mode m[4:0]
3--setting the interrupt stop bit disables the corresponding interrupt (if required)
(3) Save return address current PC to lr_<mode>
(4) Set the PC as the corresponding anomaly vector
Steps to return the exception:
(1) Recovering from spsr_<mode> CPSR

(2) Restore PC from lr_<mode>

Arm Seven exception source and exception processing flow (four steps and three steps)