Arm Study Notes Chapter 2: ARM processor fundamentals

Difference between von norann Implementation & Harvard Implementation of ARM

Von norann implementation: data items and instructions share the same bus.

Harvard implementations: It uses two different buses.

 

 

Load-store architecture:

Load: Memory ----- (load instructions copy data) -------> registers in Core

Store: registers ---- (store instructions copy data) ------> memory

There are no data processing instructions that directly manipulate data in memory.

 

Register:

There are 18 active registers available inUserMode, 16 Data Registers (R0 ~ R15) and 2 processor status registers (CPSR, spsr ).

R0 ~ R12 are general purpose registers,

R13 is stack pointer (SP ),

R14 is link register (LR, store the Reture address when a subroutine is called ),

R15 is program counter (PC, contains the address of the next instruction to be feteched .)

Sometimes R13 and 14 can be used as general-purpose registers, but using R13 is dangerous.

In arm State R0 ~ R13 are orthogonal: Any instructions that you can apply to R0 you can equally well apply to any of the other registers (R1 ~ R13 ).

 

 

Structure of SrS:

 

N z c v (j) I f t Mode

31 30 29 28 ---- 24 --------------------- 7 6 5 4----0

 

Condition flag:

N-negative: Bit 31 of the result is a binary 1

Z-Zero: The result is 0, often used in indicate equality

C-carry: an unsigned carry happens in the result

V-overflow: signed overflow happens

I: interrupt request

F: Fast inturrupt request

 

Six privileged Modes

Abort: when there is a failed attempt to access memory.

Fast interrupt: omitted

Interrupt request: omitted

Supervisor: Is the mode that the processor is in after reset and is the mode that an OS Kernel operates in.

System: a special version of user mode that allow full read-write access to CPSR.

Undefined:

Nonprivileged Mode

User: omitted

 

Interrput masks

Used to stop specific interrput requests from interrupting the processor.

Bit 7 and 6 (or I and f) are controlling the masking of IRQ and FIQ. When I bit is set to 1 IRQ is masked. So does F.

 

 

Conditional execution:

Conditional execution controls whether or not the core will execute the instruction.

The condition attribute is postfixed to the instruction mnemonic, Which is encoded into the instruction. When a condition mnemonic is not present, the defalt behavior is to set it to always execute.

 

 

Pipeline:

Using a pipeline speeds up execution by fetching the next instruction while other instructions are being decoded and executed.

 

Pipeline executing characteristics:

1. The pipeline has not processed an instruction until it passes completely through the execute stage.

2. program counter (PS) alway points to the address of the instruction plus 8 bytes (or plus two instructions ahead), because it refers to the next command to be obtained. in thumb state, it pluses 4bytes.

3. The execution of a branch instruction or branching by direct modification of PC causes the core to flush its pipeline.

4. arm10 uses branch protection by predicting possible branches.

5. An instruction in the execute stage will complete eventhough an interrupt has been raised.

 

 

Exceptions, interrupts and the vector table:

When an exception or interrupt occurs, the processor set the PC to a specific memory address which is called the vector table. the entries of this are instructions that Brach to specific routines designed to handle a special exception or interrupt.

 

 

There are 3 hardware extensions of core:

1. cache and tightly coupled memory (TCM)

2. Memory Management: 1) No extensions 2) memory Protection Unit (MPU) provides limited protection 3) Memory Management Unit (MMU) providing full protection.

3. coprocessor interface: a coprocessor extends the processing features of a core by extending the specified uciton set or by providing configuration registers.