ARM system interrupt generation process __import

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http://blog.csdn.net/mr_raptor/article/details/6556258

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The interrupt source is divided into an external interrupt source and an internal interrupt source according to the hardware location, and the external interrupt source and the internal interrupt source include the child external interrupt source and the child internal interrupt source, as shown in the figure above (painted all day).

1. Generation of child internal interrupt sources

Take the UART0 receive the data to produce int_rxd0 interrupt for example, after INT_RXD0 produces enters the SUBSRCPND child interrupt source registers the register, the setting int_rxd0 corresponding interrupt bit, interrupts the signal passes through the INTSUBMSK child Interrupt shielding register, if Int_ RXD0 signal corresponding bit has not been set (shielding), interrupt the signal to continue to pass forward, after the child internal interrupt source aggregator, the int_rxd0 polymerization of the corresponding interrupt source signal int_uart0, setting SRCPND interrupt source registers int_uart0 bit, After Intmsk interrupt shielding register, if the int_uart0 signal is not shielded, interrupt signal into the INTMOD interrupt mode register to determine whether for fast interruption, if programmed for rapid interruption, direct interrupt arm core, enter interrupt processing, if interrupt signal for general interruption, Enter the interrupt priority arbiter into the priority quorum, if the int_uart0 signal is the highest priority or only the INT_UART0 interrupt signal is generated, the interrupt signal is logged to the INTPND highest priority interrupt staging register, and the Intoffset value is set to interrupt number 28, The interrupt signal is eventually interrupted by the arm kernel for interrupt processing. If multiple interrupts are generated at the same time and int_uart0 is not the highest priority, then the interrupt signal will not be processed, and the highest priority signal is processed, and then the priority is arbitrated again, which means that the interrupt signal does not disappear and is kept in the SRCPND until it is processed.

2. Generation of internal interrupt sources

The process has been included in the sub internal interrupt processing, the interrupt signal has been generated directly into the SRCPND, and then experienced the above sub internal interrupt post-processing process.

3. Generation of child external interrupts

There are 24 external interrupt sources, where EINT0~EINT3 is an external interrupt source, eint4_7,eint8_23 is a composite interrupt source, and they contain a child external interrupt source.

Because the external hardware is directly attached to I/O Ports (see s3c2440a Hardware manual 9th), we want to let the peripheral hardware interrupt processing, first from the eint0~eint23 to select the interrupt signal, we take EINT11 as an example, introduce the child external interrupt processing process.

Usually the internal lead pins in the CPU are reused, that is to say, a CPU pin can have a variety of functions, you can set it as input signal line, output signal line or interrupt signal line, in order to let the hardware interrupt, first of all can be caused by the interruption of the PIN programming, set the PIN for the interrupt signal line. EINT11 interrupt signal corresponding to the CPU pin for GPG3, by setting gpgcon[7:6] = 0B10, you can set the PIN for the interrupt signal line.

Table 3-14 Gpgcon Registers

Set the CPU PIN for the interrupt signal line, but also by setting the EXTINT0 register to specify the trigger mode of interrupt signal: High level trigger, low level trigger, level rise along, down except along, double along the trigger.

Fig. 3-9 schematic diagram of level signal triggering

Because of the press when the key to interrupt, that is, from the high level to low power generation (the last button interrupt principle), so we set the EINT11 interrupt signal triggering method for the descent along the trigger, extint1[14:12] = 0b01x

Table 3-15 EXTINT1 Registers

After setting the triggering mode, when the level of the peripheral interrupt signal line reaches the triggering condition, the interrupt signal is generated through the external interrupt generator, and then the sub external interrupt registers the EINTPND corresponding EINT11 position 1, the interrupt signal enters the EINTMSK child external interrupt shielding register, If the EINT11 interrupt source signal is not masked, the EINT11 interrupt signal enters the sub external interrupt aggregator, which is combined into a eint8_23 interrupt signal, and then undergoes the same processing mechanism as the front child internal interrupt signal.

(1) Eintpend external interrupt staging register

Table 3-16 External interrupt staging registers (Eintpend)

Register Name	Address	whether to read or write	Description	Reset Default Value
Eintpend	0x560000a8	r/w	External interrupt Signal Staging register 0: No interrupt request signal 1: Interrupt Request signal generation	0x0000000

 

Eintpend	bit	Description	Initial value
EINT23	[23]	0 = no Interruption 1 = interrupt generation	0
...	...	...	...
EINT4	[4]	0 = no Interruption 1 = interrupt generation	0
Reserved bit	[3:0]	No	0000

(2) Eintmask external interrupt mask Register

Table 3-17 External interrupt shielding registers (Eintmask)

read/write

Register name	address	description	reset defaults
Eintmask	0x560000a4	r/w