ARM11---Interrupt---vector interrupt controller (VIC)---combined with s3c6410

2011-05-10 21:26 2527 People read review (2) Favorite report C signal interface phone

Today I looked at the ARM1176 manual about the interrupted part, it is very interesting. Write it down.

(a), first of all, say a bit PL192 vector interrupt Controller

An interrupt controller is a peripheral device used to handle multiple interrupt sources, and typically contains the following features:

1. Allocate one interrupt request input port for each interrupt source. Assign an interrupt request output port to each interrupt request to be able to connect to the VIC port of the processor.

In fact, the manual said so much, I feel that is actually the case: to ensure that each interrupt can:

************************************************

Interrupt source-------->pl192 Vic---------> processor Vic port

************************************************

2. You can use software to screen out any interrupt sources that you have made.

3. You can set a priority for each interrupt.

The above is what the interrupt controller does, but our software has to do the following:

1. Determine the interrupt source for the requested service.

2. Determine the address of the interrupt handler.

But a vector interrupt controller can implement all of the above functions on the hardware, and he can provide the starting address and vector address of the current highest-priority interrupt ISR.

PL192 Vic and processor Vic port connections:

The processor can get the current interrupted ISR via the vicvectaddrout[31:0] port, instead of using 0x00000018 or

0XFFFF0018 's strategy. However, the VIC port of the processor does not support read FIQ vector addresses.

Here is the explanation of the pin:

The irqack is a signal sent by the processor to tell Vic that I want to read the address of a interrupt handler that interrupts (IRQADDR)

Irqaddrv is a signal from Vic that tells the processor that the address of the ISR has been sent and is valid, so you can read it with confidence.

Irqack and Irqaddrv implement a four-time handshake mechanism between Vic and processor. (There is an explanation later.) ）

(ii), the exit of the interrupt handler function:

Performs a write operation on the interrupt corresponding vector address register.

(iii), the timing between the processor and Vic:

The following figure is an example of the VIC port operation timing: First with a IRQC, then a irqb, and irqb with a higher priority.

　

This diagram explains the basic handshake mechanism between the basic processor and Vic.

The 1.IRQC interrupt request was issued, causing PL192 Vic to set the processor's NIRQ to low.

2. The processor learns that NIRQ is low, and then initializes a sequence of interrupts.

3. Then at this critical time, suddenly came an interrupt irqb, which told PL192 VIC that I was more anxious than IRQC.

4. Between B3 and B4, the processor determines whether this interrupt is an IRQ or if it sends a irqack signal (high level).

5. At b4,pl192 Vic gets the Irqack high level signal and then changes the IRQADDR to the IRQB ISR address.

6. At the B6 stage, the VIC emits a IRQADDRV signal (high), and the irqaddrv is high until the processor gets the correct ISR address, even if a higher-priority interrupt is to be placed high. Otherwise, irqb this interruption

Was lost.

7. At the B8 stage, the processor reads the value of the irqaddr and reads it correctly, placing the Irqack low because his mission has been completed.

8. When PL192 Vic discovers that Irqack is low, it stacks the priority of the IRQB interrupt (this sentence is understood by everyone, should be the prioritization of the save IRQ, specifically what I still do not know. ) and then the

Irqaddrv Low, if there is no higher priority interrupt, he also put Nirq high.

9. When the processor learns that Irqaddrv is low, he knows he can detect NIRQ again, so if Vic is going to stop for a while and then set the Nirq high, the irqaddrv must be guaranteed to be high, otherwise the processor will always detect

Interrupts are the same interrupts that are emitted by the interrupt source.

We write interrupt programs to be aware of:

*************************************************************************************************************** *******************************

Interrupt handlers are guaranteed to be interrupted at the end of the program, so that multiple interrupt sources can be shared with one medium break. Additionally, the interrupt handler to notify PL192 Vic that the current interrupt of the ISR has ended.

This is the original:

The clearing of the interrupt is handled in software by the interrupt handling Routine,this enable multiple interrupt sour Ces to share a

Signal Interrupt Priority,in addition,the Interrupt handling routine must communicate to the VIC, the interrupt Curren tly being handled

is complete,using the memory-mapped or coprocessor-mapped interface,to enable the interrupt masking to be unwound.

*************************************************************************************************************** *******************************

PL192 Vic does not support fast interrupts, so the s3c6410 interrupt flowchart is drawn like this:

All the rapid interruption to VCI1, and through the VIC0, came to the TZIC0, and ultimately by the TZIC0 sent to ARM1176.

The following diagram is an interrupt sent to the executed flowchart:

This involves the conversion of the arm mode.

Here we should be aware of the process of interrupt generation and execution of interrupt handlers.

Note: VE is Vic ENABLE

MRC p15,0,r0,c1,c0,0
Orr r0,r0,# (1<<24)
MCR p15,0,r0,c1,c0,0

So our PL192 Vic can use it.

Write here today, too tired, and then write the internal interrupt (watch dog) and external interrupt (key) specific process. are based on OK6410, today is added to the theoretical knowledge.

Individuals think that these things are important to the understanding of interruptions.