Arm9-hardware interface learning 4 clock

 

By default, the operating frequency of the S3C2410 CPU is 12 MHz. The PLL circuit can generate a higher clock speed for the CPU and peripheral devices. The S3C2410 has two PLL: mpll and upll, which are dedicated to upll and USB devices. Mpll is used for CPU and other peripheral devices.

Mpll generates three clock frequencies: fclk, hclk, and Plck. Fclk is used for CPU cores, hclk is used for AHB Bus devices (such as SDRAM), and pclk is used for APB bus devices (such as UART ). You can view the hardware that uses different clock frequencies from the clock structure.

Figure 7-1. clock generator block digoal

  (Note: UART uses pclk, which will be used in subsequent UART experiments)

The following describes the mpll startup process:

(Note: The following content is directly Excerpted from the fully-developed S3C2410 process. The clock part is well written)

S3C2410 datasheet page 224"Figure 7-4. Power-On Reset Sequence"Demonstrate the mpll startup process after power-on

 

Follow the fclk image to learn about the startup process:

1. After several milliseconds of power-on, the crystal oscillator output is stable. fclk = crystal oscillator frequency. After the nreset signal is restored to a high level, the CPU starts to execute commands.

2. We canProgramStart mpll. After several mpll registers are set, it takes some time (lock time) for mpll output to be stable. During this period of time (lock time), the fclk is stopped and the CPU is stopped. The length of lock time is set by the register locktime.

3. After the lock time, the mpll output is normal and the CPU is working under the new fclk.

 

Setting the clock frequency of S3C2410 is to set the mpll registers:

1. locktime: Set it to 0x00ffffff. As mentioned earlier, after mpll is started, wait for a period of time (lock time) to make its output stable. Bit [] is used for upll, and bit [] is used for mpll. Use the saved value 0x00ffffff.

2. clkdivn: used to set the ratio of fclk: hclk: pclk. The default value is. The value here is 0x03, that is, fclk: hclk: pclk =, different clkdivn settings and corresponding clock proportions are as follows:

 

3. mpllcon: Set to (0x5c <12) | (0x04 <4) | (0x00), that is, 0x5c0040. For mpllcon registers, [] is mdiv, [] is pdiv, and [1:0] Is sdiv. The formula is as follows:

Mpll (fclk) = (M * fin)/(p * 2 ^ s), where: M = mdiv + 8, P = pdiv + 2

Fin is the default input clock frequency of 12 MHz. Mpllcon is set to 0x5c0040, and fclk = 200 MHz can be calculated. The clkdivn settings show that hclk = 100 MHz and pclk = 50 MHz.

We usually write the above clock initialization process as the clock_init function for other functions to call,CodeAs follows:

 
Void clock_init (void)

{

/* Init clock */
Rlocktime = 0 xffffff;

/* Set fclk: hclk: pclk =. In this case, if the processor clock speed is 200 m, the hclk is 50 m, and the pclk is 25 m.
Rm920t kernel uses fclk, memory controller, LCD controller, etc. use hclk, watchdog, serial port, etc. use pclk */
Rclkdivn = 0x3;

/* Set the clock frequency to 200 MB */
Rmpllcon = 0x5c0040;

}
 

Test code: Http://www.cnblogs.com/heiyue/admin/Files.aspx