Arm9_s3c2440 Learning (1) seven working modes of the arm system

7 working modes of Arm System

 

I. The CPU of the arm system has the following seven working modes:

1. User Mode (usr): normal program execution status

2. Fast interrupt mode (FIQ ):

3. interrupt mode (IRQ ):

4. Management Mode (SVC): The protection mode used by the operating system

5. System Mode (sys): Run privileged Operating System Tasks

6. Data Access termination mode (ABT): This mode is enabled when data or instruction prefetch is terminated.

7. undefined command termination mode (UND): This mode is used when undefined commands are executed.

Note:

You can switch the mode through the software, or the CPU automatically enters the corresponding mode when various types of interruptions or exceptions occur;

Except the user mode, all the other six work modes belong to the privileged mode;

The other five modes except the system mode are called the exception mode;

Most programs run in user mode;

The privileged mode is used to handle interruptions, exceptions, or access protected system resources;

2. the cpu Of the arm system is in two working states:

1. Arm

2. Thumb

CPU power-on in arm State

3. Registers

Arm has 31 General 32-bit registers and 6 program status registers, which are divided into 7 groups. Some registers are shared by all working modes, some registers belong to each working mode;

R13 -- Stack pointer register, used to save the stack pointer;

R14-program connection register. When executing the BL subroutine call command, R14 gets the R15 backup, and R14 saves the R15 return value in case of interruption or exception;

R15 -- program counter;

Fast interrupt mode has 7 backup register R8-R14, which makes it possible to go into fast interrupt mode to execute a large part of the program without even having to save any register;

Other privileged modes contain two independent register copies R13 and R14, so that each mode can have its own stack pointer and connection register;

Iv. Current Program Status Register (CPSR)

CPSR has the following meanings:

T-bit: 1--the CPU is in the thumb status,
0--cpu is in arm State;

I, F (Interrupt prohibition bit): 1 -- disable interruption, 0 -- enable interruption;

Working Mode bits: You can change these bits to switch the mode;

5. program state storage register (spsr)

When switching to a privileged mode, the spsr saves the CPSR value of the previous working mode. In this way, the spsr value can be restored to the CPSR when the previous working mode is returned;

Vi. mode switching

When an exception occurs and the CPU enters the corresponding exception mode, the following tasks are automatically completed by the CPU:

1. Save the address of the next command to be executed in the previous Working Mode in R14 of the exception mode;

2. Copy the CPSR value to the spsr in exception mode;

3. Set the CPSR working mode to the working mode corresponding to the exception mode;

4. Make the Pc value equal to the address of this abnormal mode in the abnormal vector table, that is, jump to execute the corresponding instruction in the abnormal vector table;

When the abnormal work mode is returned to the previous work mode, the software should do the following:

1. Subtract an appropriate value (4 or 8) from R14 in exception mode and assign it to the PC register;

2. Assign the spsr value of the exception mode to CPSR;