Assemble the-IA32 register organization of the speed check

Register Device	Description
General purpose Registers	8 32-bit, storing the data being processed
Segment Register	6 16-bit, processing memory access
Instruction Pointer Register	A 32-bit, pointing to the next instruction code to execute
Floating-point data registers	8 80-bit, floating point data
Control Register	5 32-bit, determine the operating mode of the processor
Debug Registers	8 32-bit, contains information when debugging the processor

Universal Registers

Register Device	Description
EAX	Accumulator for operands and result data
EBX	Pointer to data in the data memory segment
Ecx	Counters for string and loop operations
EDX	I/O pointers
Edi	Data pointer for the target of the string operation
Esi	Data pointers for the source for string manipulation
Esp	Stack pointer
Ebp	Stack data pointer

Eax,ebx,ecx,edx can be referenced by 16-bit, 8-bit name
|<------------EAX---------------->|
|-2 3 4 5 6 7 8 | 2 3 4 5 6 7 8 |
|----------------|-------|--------|
|. . . . . . . . |. AH. | . AL. |
|----------------|-------|--------|
. . . . . . . . .| <------AX------>| Segment Register

IA-32 allows 3 ways to access the system memory flat memory mode, segmented memory mode , real address mode flat memory mode: All instructions, data, stacks are contained in the same address space, access to each memory location through the linear address Segmented memory mode: Divided into 3 segments, instruction segment, data segment, stack segment, memory location is defined by logical address, contains segment address and offset address, processor converts logical address to linear address real address mode: All segment registers point to 0 linear address, so instruction, data, stack element search direct access via linear address

Segment Register	Description
Cs	Code snippet base address; The processor takes the directive based on the CS value and the offset value in the EIP
Ds	Data segment Base Address
Ss	stack segment base address; Contains data values passed to functions and procedures
Es	Additional segment pointers
Fs	Additional segment pointers
Gs	Additional segment pointer; Ds,es,fs,gs used to point to the data segment

instruction Pointer Register EIP

Trace the next instruction code, offset value or linear address to be executed; control register cannot be modified directly

Determine the operating mode of the processor the characteristics of the task currently being processed

Control Register	Description
CR0	Systems that control processor state and operating mode
CR1	Not currently used
CR2	Memory page Error message
CR3	Memory Page directory information
CR4	Flags that support processor characteristics and describe processor characteristics

Cannot read or write directly, need universal register "relay" flag bit

Each operation has a mechanism to determine whether the operation was successful
The IA-32 platform uses a 32-bit eflags containing a set of State, control, and system flags. 1. Status flag indicates the result of the mathematical operation performed by the processor

logo	bit	name	Description
Cf	0	Rounding Flag	Unsigned integer mathematical operation the most significant bit yields rounding or borrowing, set 1
Pf	2	Parity Check Flag	Odd check digit, which makes the register and the number of this bit 1 is an odd number
Af	4	Auxiliary carry Flag	For BCD math operations
Zf	6	0 symbols	Operation result is 0, set 1
SF	7	Symbol sign	Set to the most significant bit of the result
Of	11	Overflow flag	The number of characters with a positive value is too large or negative over the hour, overflow

2. Control flags control the specific behavior of the processor.

Currently only one control flag-DFF flag (direction flag) is defined, controlling how the processor handles the string

DF Set (set 1) string instruction automatically low decrement memory address one reaches the next byte of the string

DF bit Clear 0 (set 0) string instruction automatically low increment memory address one reaches the next byte of the string 3. System flags control operation at the operating system level.

Applications should not attempt to modify system flags

logo	bit	name	Description
Tf	8	Trap Flags	1 o'clock, enable single-step mode, execute one instruction at a time, wait for the next instruction to execute the signal. Very useful when debugging assembler
IF	9	Interrupt Enable flag	Control how the processor responds to signals received from an external source
IOPL	12 and 13	I/O privilege level flags	Indicates the I/O permission level for the currently running task
Nt	14	Nested task Flags	Controls whether the currently executing task is linked to a previously performed task. Used to link interrupted and called tasks
RF	16	Restore Flag	Control how the processor responds to exceptions in debug mode
Vm	17	Virtual 8086 status Flag	Indicates that the processor is executing in the virtual 8086 state, not the protected mode real or mode
AC	18	Alignment check mark	With CR0 's AM bit to enable alignment checking of memory references
VIF	19	Virtual Interrupt Flag	When the processor operates in virtual mode, it acts as an if flag bit
Vip	20	Virtual Interrupt Suspend flag	Flag an interrupt is being suspended while the processor is operating in virtual mode
Id	21st	Identification Mark	Indicates whether the processor supports CPUID instructions

Reference:
64-ia-32-architectures-software-developer-vol-1-manual
IA32 instruction Set
"Assembly Language Program Design" Richard Blum