- A typical CPU consists of an operator, a controller, a register, and other devices that are connected to the internal bus. In the first chapter, the bus is the external bus relative to the internal CPU. The internal bus realizes the connection between each device inside the CPU, and the external bus realizes the connection between the CPU and other devices on the motherboard. To put it simply, in the CPU:
- Computing device for information processing;
- Register for information storage;
- The controller controls various devices to work;
- The internal bus links various devices and transmits data between them.
- For a assembler programmer, the main component in the CPU is the register. Registers are parts of the CPU that programmers can read and write with instructions. Programmers can control the CPU by changing the contents of various registers.
Different CPUs, the number of registers, the structure is not the same. 8086CPU has 14 registers with a name for each register. These registers are: AX, BX, CX, DX, SI, DI, SP, BP, IP, CS, SS, DS, ES, PSW.
- General purpose Registers: AX, BX, CX, DX, these 4 registers are usually used for storing general data.
- 8086CPU of the previous generation of the CPU registers are 8-bit, in order to ensure compatibility, so that the original program based on the CPU written by a slight modification can be run above 8086, 8086CPU Ax, BX, CX, DX 4 registers can be divided into two independent use of 8-bit registers to use:
- Ax can be divided into Ah and al;
- BX can be divided into BH and BL;
- CX can be divided into ch and cl;
- DX can be divided into DH and DL;
- For compatibility reasons, 8086CPU can process data in the following two sizes at once:
- Byte: In bytes, a byte consists of 8 bits and can exist in a 8-bit register.
- Word: Recorded as Word, a word consists of two bytes, these two bytes are called the word's high-order byte and low byte.
- In order to distinguish between the different binary, the hexadecimal representation of the data after the H, after the binary representation of the data plus B, the decimal representation of the data after nothing is added. For example: decimal: 20000, 16 binary: 4e20h, binary: 0100111000100000B.
- Physical Address: All memory units consist of a one-dimensional linear space, and each memory unit has a unique address in this space, and we call this unique address a physical address.
- 16-bit structure: a 16-bit structure (16-bit machine, 16-bit word length, and so on, and the meaning of the 16-bit structure) describes a CPU has the following aspects of the structural characteristics:
- The operator can process up to 16 bits of data at a time;
- The maximum width of the register is 16 bits;
- The path between the register and the operator is 16 bits.
- 8086 is a 16-bit structure of the CPU, which means that within 8086, the maximum length of information that can be processed, transmitted, and temporarily stored is 16 bits. The address of the memory unit must be processed, transmitted, and temporarily stored in the CPU before address bus, and for 16-bit CPUs, it can process, transmit, and temporarily store 16-bit addresses.
- Logical structure of 8086CPU related parts:
As shown in 2.6, when 8086CPU reads and writes memory:
(1) The relevant parts of the CPU provide two 16-bit addresses, one is called the segment address, the other is called the offset address;
(2) The address and the offset address are fed into a part called the address adder via the internal bus;
(3) The address adder will combine two 16-bit addresses into a 20-bit physical address;
(4) The address adder feeds the 20-bit physical address into the input-output control circuit via the internal bus;
(5) The input and output control circuit sends the 20-bit physical address to the address bus;
(6) The 20-bit physical address is transmitted to the memory by the address bus.
The address adder uses the Physical address = Segment Address x16+ offset address to synthesize the physical address with the segment address and offset address.
- The essential meaning of "segment address x16+ offset address = Physical Address" is that when the CPU accesses memory, it adds a base address (segment address x16) and an offset address relative to the base address to give the physical address of the memory unit.
More generally, this addressing feature of 8086CPU is a concrete implementation of "base address + offset address = Physical Address" addressing mode.
- Memory is not fragmented, the segment is divided from the CPU, because 8086CPU with "base address (segment address x16) + offset address = Physical Address" to give the physical address of the memory unit, so that we can use a segmented way to manage memory.
- When programming, it is possible to treat several contiguous memory units as a segment, with the segment address x16 the starting address of the locating segment (the base address), and the offset address to locate the memory unit in the segment. There are two points to note:
- Segment Address x16 must be a multiple of 16, so the starting address of a paragraph must also be a multiple of 16;
- The offset address is 16 bits and the 16-bit address has a 64KB addressing capacity, so the length of a segment is 64KB maximum.
- "The data is in the 21F60H memory unit. "This sentence for the 8086CPU machine is not generally said, replaced by two similar statements: ① data exists in memory 2000:1f60 unit, ② data exists in the memory of the 1F60 unit in 2000 segments. Both of these descriptions represent "data in memory 21f60 units".
- You can define a set of memory units as a multiple of a contiguous address, starting at 16, as needed, as a segment.
- 8086CPU has 4 segment registers: CS, DS, SS, ES.
- In 8086, at any moment, the CPU will cs:ip the content pointed to as instruction execution.
- The working process of 8086CPU can be briefly described as follows:
- Read the instruction from the memory unit pointed to by the CS:IP, and read the instruction into the instruction buffer;
- ip=ip+ the length of the instruction to be read, thus pointing to the next instruction;
- Execution instructions. Go to step 1 and repeat the process.
- After the 8086CPU power on or reset (that is, when the CPU is just starting to work) CS and IP is set to cs=ffffh,ip=0000h, that is, when the 8086PC machine starts, the CPU reads instructions from the memory ffff0h unit, The instruction in the FFFF0H unit is the first instruction executed after the 8086PC machine is powered on.
- In memory, there is no difference between the instruction and the data, it is binary information, the CPU in the work of the information as a command, and some information as data. The CPU treats the contents of the memory cells pointed to by the Cs:ip as instructions, because at any time the CPU treats CS, the contents of the IP as the segment address and offset address of the instruction, uses them to synthesize the physical address of the instruction, reads the instruction code in memory, executes.
If, in memory, a piece of information has been executed by the CPU, then the memory unit in which it resides is bound to be pointed to by CS:IP.
- The instructions that can change the contents of CS and IP are collectively referred to as transfer instructions.
The function of the "JMP segment Address: Offset address" Directive is to modify CS with the segment address given in the instruction, offset address to modify IP.
If you want to modify only the contents of the IP, you can use the form "a valid register in JMP" to complete the instruction function: Modify the IP with the value in the register.
- Code snippet: For a 8086PC machine, when programming, you can define a set of memory cells as a segment as needed. We can put a set of code of length N (N≤64KB), there is a set of contiguous address, starting address is a multiple of 16 memory units, we can think that this memory is used to store code, thus defining a code snippet.
How do I make the instructions in the code snippet execute? Treating a piece of memory as a code snippet is just an arrangement that we are programming, and the CPU does not automatically execute the instructions in the code snippet we define as an instruction because of this arrangement. The CPU only recognized that the contents of the memory unit pointed to by CS:IP are directives. So, to get the CPU to execute the instructions we put in the code snippet, we have to point Cs:ip to the first address in the code snippet that we defined.
| 2.9~2.12 summary |
| (1) The address is stored in the 8086CPU segment register. When 8086CPU accesses memory, the segment register provides the segment address of the memory unit.  8086CPU has 4 segment registers, where CS is used to store the segment address of the instruction. |
(2) CS holds the segment address of the instruction, and IP holds the offset address of the instruction.
8086, at any time, the CPU will be Cs:ip point to the content as instruction execution. |
(3) 8086CPU working process:
 ②IP refers to the next instruction,
③ execution instructions. (Go to step ① and repeat the process.) |
| (4) 8086CPU provides transfer instructions to modify CS, IP content. |
- Debug Program: Debug is a debug tool that DOS, Windows provides real mode (8086-way) programs. With it, you can view the contents of various registers of the CPU, the situation of memory and the operation of the machine code level according to the program.
- During the learning process, the debug functions used (more than 20, the following are common commands):
- Use the Debug R command to view and change the contents of the CPU register;
- Use Debug D command to view the contents in memory;
- Overwrite the contents of the memory with the Debug E command;
- Use the Debug U command to translate the in-memory machine instructions into assembly instructions;
- Execute a machine instruction with the T command of debug;
- Write a machine instruction in memory with the debug a command in the format of the assembly instruction.
- Enter debug: "Start"-"Run"-enter "command", OK-and enter the DOS, input Debug.
assembly Language Basic Knowledge Abstract ("assembly language" Wang Shuang) 2nd/17 Chapters
