Assembly language Instruction

assembly language in the source program to express instructions in statements, there are three basic types of statements:

1, the instruction : The assembly forms a machine language instruction, between them is one by one corresponds, in the program execution time instruction executes.

2, pseudo-directive : Just tell the assembler how to do the assembly, the Assembly did not generate machine language instructions, he was in the Assembly of the implementation.

3, macro : It is defined by the user's own instructions, consisting of instructions and pseudo-instructions, he is in the process of assembly, macro expansion, with the corresponding instructions and pseudo-instructions to replace the macro instructions.

1/1, the composition of the statement in assembly language

　　The statements in assembly language consist of the following four parts:

　　　Name space or: operation mnemonic spaces;

Note: Each statement can have a name, or it can have no name. This type of name has two meanings:

1. Marking: When the name in the statement is separated from the mnemonic by a colon, the name represents a label that represents the address (segment address, offset address) of the instruction.

2. Variable name: When a space interval between a name and a mnemonic in a statement, the name represents the variable name that represents the storage space where the data is stored.

1/2. Constants and expressions in assembly language

Constant:

Values: B (binary), D (decimal), H (hexadecimal)

String: Inside the single quotation mark, representing the ASCII code of each character

Expression: consists of operands and operators

　　

""" arithmetic operators: + 、-、 *,/, MoD logic operators:  and OR   not  xor relational operator: EQ (equal),  EN (unequal)                  LT (less than),  GT (greater than)                  LE (less than equals), GE (greater than equals)"" "             

1/3 Marking, variable

# The label is used to indicate the address of the corresponding instruction, with a colon interval between the mnemonics Example:    Start:mov Ax, Note: The label START represents the address of the     instruction "Start:mov AX,1000", so that you can use the transfer statement in JMP START to transfer to a change address.

# variables are defined by a pseudo-directive, with spaces instead of colons : variable names db/dw/dd/dq/dt expressions  ; definitions (8/16/32/64/80) Note     :1, variable name is optional    2, one or more expressions or constants separated    by commas 3, one, multiple question marks (?). ), which indicates that only the variable is allocated a    storage space of 4, repeating the way, when the form of the expression is the number of repetitions of the                                                    DUP (expression)
5, $ when appearing in an expression, represents the offset address of the current Assembly statement
6. Special usage of pseudo-directive DW DD
The pseudo-directive DD DW can also be used to preset the variable's offset address in addition to the defined variable

Example: AD2 DW AD1  ; AD2 point to AD1 start address
DD usage format is the same as the above usage
Example: AD4 DD AD1  

1/4 attribute operators and PTR operators

The PTR operator can be used to temporarily change the type of a variable or label that has already been defined (including byte-byte, Word, DWORD, or label-type near-to-FAR)

Use format: type PTR expression

　　

# attribute operator SEG take out the              segment address offset take out        the offset address type take out             its type length take        out the variable number of repetitions              size of the variable

2/1 how data is addressed to the transfer address

1. How to address data: Find out how to manipulate the data required by the instruction

2, the transfer address of the addressing mode: to find the transfer instructions required program address method

#how data is addressedThere are 8 common data addressing methods for 8086CPU instruction systems: Immediate addressing, register addressing, memory Addressing (5 types: Direct addressing, register indirection, register relative addressing, base address address, address change address, and relative addressing), Implicit addressing the following are some examples of the more difficult to understand addressing:#Register relative addressingMOV CX,VAR1[BX]; (CX) <--(BX) +OFFSET VAR1) MOV Al,var2[di-15]; (AL) <--((DI) + (OFFSET var2-15)) MOV5[SI+24],DX;((SI) + (5+24)) <--(DX)#base Address variable address addressingMOV Dx,[bx][si];(D x) <--((BX) +(SI)) MOV Ax,[bp][si];(AX)<--(BP) +(SI)) BP default segment address in SS segment#base Address variable address and relative addressingMOV Var1[bp][di],ax;((BP) + (DI) +offset VARI) <--AX#Implicit addressingMOVSB; instruction meaning: Remove a byte from the storage unit (DS:SI), transfer to the (ES:DI) storage unit, and the contents of SI and DI automatically increase by 1 (when df=1), or automatically minus 1 (when df=1 o'clock)#addressing the transfer addressThere are 4 ways of addressing the transfer address: the direct and indirect way, the direct and indirect way in the segment

2/1

data transfer class directive : General Delivery class instruction MOV

Get valid address directive LEA

Get address pointer instruction LDS, LES

Flag delivery instruction LAHF, SAHF

Data exchange Directive XCHG

BYTE conversion instruction XLAT

Stack operation instruction PUSH, POP, PUSHF, Popf

#General Delivery Instructionsformat mov dst,src; Description: Transfers one byte or one word from the source operand to the location specified by the destination operand. Note: The MOV instruction cannot be connected directly to the path: (1), The Register of registers (2), Storage unit storage unit (3), segment Register segment register if you want to complete the above data transfer, you can complete the following steps for the immediate number--General Register--Segment Register"""MOV Ax,3a01hmov Ds,ax"""Storage Unit--General Register--Storage Unit"""MOV Ax,var1mov Var2,ax"""Segment Register--General Register--Segment Register"""MOV Ax,csmov Ds,ax"""(CS Register cannot be used as the destination register) for a dual-action instruction, the two operand types must match:~Both types are specified, they must be the same, otherwise an error~One of the two specifies the type, and the general instructions are flawless~both have no type, then the instruction error is for the type of operand~the immediate number is no type~direct addressing without variable names, register relative addressing, register indirection, base address addressing, base address address, and relative addressing operand are also untyped~Use the PTR operator to specify or temporarily change the type of the storage unit from the formal view, immediately the number is: an expression consisting of constants, all attributes of the label or variable obtained by the attribute operator (OFFSET SEG LENGTH type, etc.)

MOV

1 #take effective address command Lea2 format: LEA reg16,mem3 Note: The effective address command Lea can feed the valid address of the source operand to the 16-bit register REG16, which transmits not the contents of the MEM (memory unit) but the valid address of the storage unit. Here the source operand mem can only be a direct addressing method4 5 For example:6 LEA di,var1: equivalent to MOV di,offset VAR17LEA bx,var1+158 9 #fetch address pointer command LDS LESTenFormat: LDS Reg16,mem:(DS) <--(mem+2), (REG16) <--(MEM) OneLES Reg16,mem:(ES) <--(mem+2), (REG16) <--(MEM) A Note: The fetch address instruction LDS can send the high 16 bits of the double-byte variable mem content into the DS, the lower 16 bits into the specified REG16, the address instruction Les can feed the high 16 bits of the double-byte variable mem content into ES, and the low 16 bits into the specified REG16. -Note: The REG16 here are not allowed for segment registers

LEA LDS LES

1 format: lafh    ;(AH) <--PSW Register low 8-bit 2           SAHF    ; The low 8-bit <--(AH)3 Description of the PSW register: instruction LAHF can transfer the low 8 bits in the PSW register to the bootcamp AH, while the instruction    SAHF can transmit the content of AH to the lower 8 bits of the PSW register. Both the source operand and the destination operand are addressed in an implicit addressing manner

LAHF SAHF

1 # data exchange Directive XCHG 2 format: XCHG dst,src   ;dts<-->SRC3 Description: The data exchange instruction completes the exchange of data between the two operands, but the two cannot be a storage unit at the same time. The XCHG instruction can complete the exchange of content between registers and registers, registers, and storage units, but it should be noted that segment registers cannot be used here.

XCHG

1 #byte conversion directives2Format: XLAT;(AL) <--((BX) +(AL))3Description: Byte conversion instruction Xlat can bx+ a valid addressThe contents of Al's storage unit are fed into AL. When the input is a byte (the contents of al), the output is also a byte (also stored in AL)4 Example:5 in the DS segment:6             7 TABLE DB 30h,31h,32h,33h,34h8 in CS segment:9MOV al,4Ten LEA bx,table One XLAT A  - " "that is, the al=34h character ' 4 '" "

XLAT

1 #Stack Operation directives2 The stack must be manipulated by word! And the operand cannot be an immediate number3 The segment address of the stack is specified by the SS, and the offset address of the stack is specified by the SP4 5 format: PUSH SRC6 PUSHF7 POP SRC8 Popf9             Ten Description: Presses SRC into the stack One Press the contents of the PSW onto the stack A Pop a word from the stack into SRC - popped a word from the stack fed to the PSW -             

PUSH POP PUSHF Popf

2/2

Arithmetic Operation class directives:

Add and subtract instruction add ADC INC SUB SBB DEC NEG

Compare instruction CMP

Multiplication method directive MUL Imul DIV Idiv

Symbol extension Directive CBW CWD

BD number Operation tuning instruction AAA DAA AAS DAS AAM AAD

# addition instruction add ADC format: Add dst,src    ;(D st) <--(SRC) +(DST)         ADC dst,src    ;(D St)<--(SRC) + ( DST) +(CF) Description: ADC is an addition instruction with carry Add ADC directive will normally affect the 6 status flag bits in the PSW: CF AF of SF-PF# incremental instruction INC DST    ;(D St The <--(DST) +1Inc directive can affect the 5 flag bits in the PSW, but does not affect the CF bit.  # Subtraction Instruction Sub SBB format: Sub dst,src         SBB dst,src Description: Same addition # decrement instruction  Format: DEC DST Description: same addition

ADD ADC INC SUB SBB DEC NEG

1 #Compare Directives2Format: CMP dst,src;(D St)-(SRC), and set the status flag bit in the PSW3Description: (DST)-(SRC), and sets the status flag bit in the PSW, but its result is not saved to DST. CMP directive affects 6 status flag bits in the PSW4 The main purpose of a CMP operation on two numbers is to compare the size and equality of two numbers5~ If two numbers are equal, then zf=16~SF equals the highest bit7~Depending on the case, CF of8 when a two unsigned number is compared,9If cf=0 zf=0 means dst>SRCTenIf Cf=1 represents dst<SRC One when two signed numbers are compared, AOf=1 indicates that the operation produced an overflow, but the size of the comparison to be determined by the of and SG, when the of with the SF = = 0 o'clock, DST >=src, when the SF is 1 o'clock, dst<src

CMP

Microprocessor status word PSW each flag bit (9):

CF: Carry flag D7 or D15 with or without carry, with rounding cf=1

PF: The low 8 bits of the result of the parity flag operation contain the number of ' 1 ', an even number of 1, an odd number of 0

AF: Auxiliary carry flag D3 bit no carry, carry af=1

ZF: 0 Flag bit operation result is 0 o'clock Zf=1

SF: Symbol flag operation result is negative sf=1

Of: Overflow flag overflow of=1

DF: The contents of the Df=0 Register (SI,DI) increment when the direction flag is changed

TF: When the trap flag is tf=1, the CPU is in single step execution mode

If: Interrupt allowed flag if=1, CPU can respond to interrupt request

Two-point description:

As long as the CPU is involved in the operation, the result will affect the status flag

Segment registers cannot participate in operations

　　　

Assembly language Instruction