Assembly Language Learning Note (ii): register (CPU operating principle)

How CPUs work
The CPU is composed of devices, controllers, registers, etc., which are connected by the internal bus
2.1 General-Purpose registers
8086 has 14 registers (16-bit): AX,BX,CX,DX,SI,DI,SP,BP,IP,CS,SS,DS,ES,PSW
AX,BX,CX,DX is called a general-purpose register to hold general data, and to ensure backwards compatibility, the universal register can be divided into two independent 8-bit registers.
Example: Ax:ah and Al (High-low)

2.2 Words in the storage of registers (a word of two bytes)
2.3 Assembly Instructions: Case insensitive
MOV ax,18 will be 18 fed into AX
Add ax,18 adds 8 to the value in register AX
2.4 Physical Address
All memory units are composed of a one-dimensional linear space of storage space
16-bit:
The operator can handle up to 16 bits of data at a time
The maximum width of the register is 16 bits (universal Register)
The path between the register and the operator is 16 bits.
8086 has 20-bit address bus, can transmit 20-bit address, addressing capacity of 1M
8086 internal is a 16-bit structure, can only transmit 16-bit address, the expression of the ability only 64k;8086 in the internal with two 16 bits (segment address and offset address) to synthesize a 20-bit: Physical address = Segment Address *16+ offset address
2.5
2.6
2.7 Segment (very important)
The memory is not fragmented, the segment is divided from the CPU, since 8086CPU is used for physical address = Segment Address *16+ offset address
1) The starting address of a segment must be a multiple of 16
2) The offset address is 16 bits, the 16-bit address has a 64k addressing capacity, so the maximum length of a segment is 64k
2.9 Segment Registers
8086 main four segment registers: CS, Ds,ss,es
8086CPU to access memory, there are four memory units that provide the segment address of a memory unit
CS: For code segment Register (segment address)
IP: For instruction pointer register (offset address register)
CS and IP are the most critical registers in 8086, and they indicate the address at which the CPU is currently reading instructions
Also modify the content in Cs:ip: jmp 2ae3:3

2.12 Code Snippets
A set of code with a length of n<=64kb, a set of memory cells with a multiple of the address contiguous, starting at 16, is used to hold the code, which defines a code snippet.

Debug command
R: Change the contents of the CPU register (R AX)
D: See what's in memory
E: command to overwrite contents in memory
U: Translate in-memory machine instructions into assembly instructions
T: Execute a machine instruction
A: Write a machine instruction in memory in the format of the assembly instruction

MOV ax,1000h
MOV Ss,ax
MOV sp,0010h
PUSH AX
PUSH BX
PUSH DS