Assembly Tutorial: Control registers and system address registers

The 80386 control registers and the system address registers are shown in the following table. They are used to control the working mode, control the subsection management mechanism and implement the paging management mechanism.

Control Register	CRx	BIT31	Bit30-bit12	Bit11-bit5	BIT4	BIT3	BIT2	BIT1	BIT0
CR0	Pg	0000000000000000	Et	Ts	Em	Mp	PE
CR1	Keep
CR2	Page Fault linear address
CR3	Page Catalog Table physical page number	000000000000

Bit47-bit16	Bit15-bit0
Global Descriptor Tabulation Register GDTR	Base Address	Boundaries
Interrupt Descriptor Tabulation Register IDTR	Base Address	Boundaries

bit15-bit0 local descriptor register LDTR select child select child

Bit31-bit0 Bit31-bit0 Bit11-bit0 Base Address Boundaries Property Base Address Boundaries Property

< one > control registers

Visible from the table above, 80386 has four 32-bit control registers, named Bit CR0, CR1, CR2, and CR3 respectively. However, CR1 is reserved for future processors to use, CR1 cannot be used in 80386, or it can cause invalid instruction to operate abnormally. CR0 includes control bits that indicate how the processor works, including control bits that enable and disable paging management mechanisms, and control bits that control the operation of floating-point coprocessor. CR2 and CR3 are used by the paging management mechanism. Bits 0 to 11 in bits 5-bit 30 and CR3 in CR0 are reserved bits, which cannot be random values and must be 0.

The lower 16 bits of the control register CR0 equal to 80286 of the machine state character MSW.

1. Protection control Bit

The bit 0 in the control register CR0 with the PE tag, bit 31 with the PG tag, which controls the operation of the segmentation and paging management mechanisms, so they are called protection control bits. PE control subsection management mechanism. Pe=0, the processor runs in real mode; pe=1, the processor runs in a protected manner. PG controls paging management mechanism. Pg=0, disables the paging management mechanism, at this time the linear address which the subsection management mechanism produces is used directly as the physical address, pg=1, enables the paging management mechanism, at this time the linear address through the paging management mechanism transforms the bit physical address. A detailed introduction to the paging management mechanism is given in a later article.

The following table lists the working methods of the processors selected by using the PE and PG bits. Because the paging mechanism can only be enabled in a protected manner, although there are four combinations of two digits, 0 and 1, only three combinations are valid. Pe=0 and pg=1 are invalid combinations, so loading the CR0 registers with a value of PG 1 and PE 0 will cause a generic protection exception.

It is important to note that the change in PG position enables the system to enable or disable the paging mechanism so that the PG bit can be changed only if the code of the program executing and at least some of the data has the same address in the linear address space and the physical address space.

PG and PE Bit and place Working with the manager As a mode	Pg	PE	How the processor works
0	0	Real mode
0	1	Protection mode, disabling paging mechanism
1	0	Illegal combination
1	1	Protection mode, enable paging mechanism

2. Co-processor control bit

The bit 1-bit 4 in the control register CR0 are labeled MP (arithmetic presence), EM (analog bit), TS (task switching bit) and ET (extended type bit), which control the operation of the floating-point coprocessor.

When the processor is reset, the ET bit is initialized to indicate the type of digital coprocessor in the system. If there are 80387 coprocessor in the system, then et position 1; If there are 80287 coprocessor or no coprocessor in the system, then et is 0.

The execution of the EM bit control floating point instruction is performed by software simulation or by hardware. When em=0, a hardware-controlled floating-point instruction is transmitted to the coprocessor; em=1, the floating-point instruction is simulated by the software.

The TS bit is used to speed up task switching, which is achieved by means of coprocessor switching when necessary. The processor resets the TS to 1 whenever a task is switched. When Ts=1, a floating-point instruction produces a device unavailable (DNA) exception. The MP bit controls whether the wait instruction produces DNA abnormalities when ts=1. When Mp=1 and Ts=1, wait produces an exception; mp=0, the wait instruction ignores TS conditions and does not produce an exception.

3.cr2 and CR3

Control registers CR2 and CR3 are used by paging management mechanisms.

CR2 to report an error message when a page exception occurs. When a page exception occurs, the processor stores the linear address that caused the page exception in CR2. The page exception handler in the operating system can check the contents of the CR2 to detect which page in the linear address space causes the exception.

CR3 is used to save the beginning physical address of the page catalog table. Because the directory is page-aligned, it is only 20-bit high and the low 12-bit retention is not available. When a new value is loaded into the CR3, the lower 12 bits must be 0, but the low 12 bits are ignored when the value is taken from the CR3. Each time the CR3 value is reset with the Mov command, the contents of the paging mechanism cache are invalidated, and this method allows you to refresh the paging mechanism cache before the paging mechanism is enabled, that is, before the PG position 1. CR3 registers can be mounted even if the PG bit or PE bit of the CR0 register is 0 o'clock, such as CR3 can be set in real mode to initialize the paging mechanism. When a task switches, CR3 is changed, but if the CR3 value in the new task is the same as the CR3 value in the original task, then the processor does not flush the paging cache so that it has a faster execution speed when the task shares the table.

< two > System address register

Global descriptor Tables GDT, local Descriptor Table LDT and interrupt descriptor IDT are very important special sections in the protection mode, they contain important forms for segment mechanism. To easily locate these segments quickly, the processor uses special registers to hold the base address and segment boundaries of these segments. We refer to these special registers as system address registers.

1. Global Descriptor Tabulation Register GDTR

As shown in the table at the beginning of this article, the GDTR is 48 bits long, with a high 32-bit base address and a low 16-bit limit. Since GDT cannot be defined with descriptors within the GDT itself, the processor uses GDTR to provide a pseudo descriptor for GDT this particular system segment. GDTR given the GDT, as shown in the following figure.

The segment bounds in the Gdtr are in bytes. Because only 13 bits in the segment selector are indexed as descriptors, and each descriptor is 8 bytes long, the 16-bit bounds are sufficient. Typically, the segment bounds for a descriptor containing N descriptors are set to 8*n-1.

Use struct types to define pseudo descriptors as follows:

PDESC STRUC　　 LIMIT DW 0　　 BASE　DD 0　　 PDESC ENDS 2. Local Description Chart Register LDTR

The local Descriptor Chart Register LDTR The local descriptor Ldt used by the current task. As shown in the table at the beginning of this article, LDTR is similar to a segment register, consisting of 16-bit registers that are visible to programmers and cache registers that are not visible to programmers. In fact, the local descriptor chart for each task Ldt as a special segment of the system, described by a descriptor. Descriptors for descriptor Ldt are stored in GDT. In the initialization or task switching process, the descriptor corresponding to the task Ldt of the descriptor of the selection of LDTR, the processor according to the LDTR visible part of the selection, from the GDT to take out the corresponding descriptor, and the LDT base address, Information such as bounds and attributes is saved to a LDTR cache register that is not visible. Subsequent visits to the LDT can be checked for legality according to the information stored in the cache.

The LDTR register contains the LDT selection of the current task. Therefore, the selector that is mounted to the LDTR must determine a system segment descriptor in the GDT type LDT, or the TI bit in the selector must be 0, and the Type field in the descriptor must be LDT.

You can mount LDTR with an empty selector, which means that the current task has no LDT. In this case, all the selectors that are loaded into the segment register must indicate the descriptor in the GDT, i.e. the segments involved in the current task are described by descriptors in GDT. If the selection of a TI bit 1 is loaded into the segment register, it will cause an exception.

3. Interrupt Description Tabulation Register IDTR

Interrupt Descriptor Register IDTR point interrupt descriptor IDT. As shown in the table at the beginning of this article, the IDTR is 48 bits long, 32 of which are based on the base address of the IDT, and the 16-bit boundary stipulates the IDT segment. Since 80,386 supports only 256 interrupts/exceptions, the maximum length of the IDT table is 2K, with a segment bound to 7FFH in byte-bit units. IDTR indicates IDT in the same way as GDTR indicates GDT.

4. Task Status Segment Register TR

Task State Segment Register TR contains a descriptor selector that indicates the task status segment that describes the current task, which specifies the status section for the current task. The format of the task Status section is described in a later article. As shown in the table at the beginning of this article, TR also has two parts that are visible and invisible to programmers. When the selection of the task status segment is loaded into the TR visible part, the processor automatically saves information such as the Janki address in the descriptor index of the selected child to an invisible cache register. After that, access to the current task status section can be done quickly and easily. The selector that is loaded into TR cannot be empty, the descriptor in GDT must be indexed, and the type of the descriptor must be TSS.