Asynchronous FIFO Verilog code comment analysis

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This asynchronous FIFO, depth 256, width 8;
a similar array, with an array example: depth 256, indicating that the array holds 256 data, and a width of 8, indicating that each data is a 8-bit binary;

Using gray code to judge the condition of empty and full,
The reason is gray code adjacent data only change one, can reduce the adjacent physical signal line changes simultaneously, reduce the possibility of circuit crosstalk, reduce the noise in the circuit.

Attention:
Gray code empty, directly determine whether the read and write address is the same;
Gray code is full, need to meet the conditions: The highest bit is different, the second high is also different, the rest must be the same; therefore, the signal needs to be turned up 2 bits, the rest is unchanged;

Module FIFO (wr_clk,//write FIFO clock nWr,//write FIFO signal Din,//write FIFO data rd_clk,//read FIFO CLO CK nRd,//read FIFO signal Dout,//read FIFO data full,//1 = FIFO full empty);//1 = FIFO Empty INP
 UT wr_clk, NWr, RD_CLK, nRd;
 input [bsize-1:0] Din;
 Output [bsize-1:0] Dout;

 Output full, Empty;
 Reg Full, Empty; reg [bsize-1:0] Buff [dsize-1:0];//fifo storage space, can be seen as an array of Reg [asize:0] wr_addr_bin, rd_addr_bin;//write, read address (binary)//write, read address (gray code) ; Used to judge the empty, full flag;//binary adjacent two, may need to change the number of bits at the same time, and the use of gray code is because the transformation of adjacent gray code to change only one, to avoid the metastable occurrence;//therefore need to convert binary address (easy to understand) to Gray code address (secure data) reg [asize:0]
 Sync_wr_addr0_gray, Sync_wr_addr1_gray, Sync_wr_addr2_gray;

 reg [asize:0] Sync_rd_addr0_gray, Sync_rd_addr1_gray, Sync_rd_addr2_gray;
 Wire [asize-1:0] fifo_entry_addr, fifo_exit_addr; Wire [asize:0] Wr_nextaddr_bin, the address of the rd_nextaddr_bin;//asize+1 bit, the highest bit used to mark the number of flips, auxiliary judgment empty full sign wire [asize:0] Wr_nextaddr_gray,
 Rd_nextaddr_gray;

 Wire Asyn_full, Asyn_empty; Parameter dsize = Asize = 8, bsize= 8;//dsize indicates the depth of the FIFO (the amount of data that can be stored), Asize represents the address bit width, and bsize represents the width of the FIFO (that is, the data is several).
  Here is the initialization of the FIFO initial begin full = 0;

  Empty = 1;
  Wr_addr_bin = 0;

  Rd_addr_bin = 0;
  Sync_wr_addr0_gray = 0;
  Sync_wr_addr1_gray = 0;
  Sync_wr_addr2_gray = 0;
  Sync_rd_addr0_gray = 0;
  Sync_rd_addr1_gray = 0;
 Sync_rd_addr2_gray = 0; End////////////////////fifo Write and output of data//////////////////////////////////////Assign FIFO_EXIT_ADDR = Rd_Addr_Bin[
 ASIZE-1:0];

 Assign fifo_entry_addr = wr_addr_bin[asize-1:0]; Assign Dout = buff[fifo_exit_addr];//Read data always @ (Posedge wr_clk)//write data begin if (~NWR & ~full) Buff[fifo_entry_ad
  Dr] <= Din;
 else buff[fifo_entry_addr] <= buff[fifo_entry_addr]; End///////////////////fifo read-write Address generator///////////////////////////////////////Assign Wr_nextaddr_bin = (~nWr&~Full ) ?
 WR_ADDR_BIN[ASIZE:0]+1:WR_ADDR_BIN[ASIZE:0]; Assign Rd_nextaddr_bin = (~nrd&~empty)?

 RD_ADDR_BIN[ASIZE:0]+1:RD_ADDR_BIN[ASIZE:0]; Assign Wr_nextaddr_gRay = (wr_nextaddr_bin >> 1) ^ wr_nextaddr_bin;//binary converted to gray code, move right one and bitwise XOR with yourself.

 Assign Rd_nextaddr_gray = (rd_nextaddr_bin >> 1) ^ rd_nextaddr_bin;
  Always @ (Posedge wr_clk) begin Wr_addr_bin <= Wr_nextaddr_bin;
 Sync_wr_addr0_gray <= Wr_nextaddr_gray;
  End always @ (Posedge rd_clk) begin Rd_addr_bin <= Rd_nextaddr_bin;
 Sync_rd_addr0_gray <= Rd_nextaddr_gray; End///////////////////uses dual latches to synchronize asynchronous signals/////////////////////////////always @ (Posedge wr_clk) begin Sync_rd_addr2_gra
 Y <= sync_rd_addr1_gray;//Read signal synchronization to write clock Sync_rd_addr1_gray <= Sync_rd_addr0_gray; End always @ (Posedge rd_clk) begin Sync_wr_addr2_gray <= sync_wr_addr1_gray;//write signal sync to read clock Sync_wr_addr1_gray <
 = Sync_wr_addr0_gray; End/////////////////will produce the full signal and the Empty signal synchronously on the respective clock domain//////////////assign asyn_empty = (rd_nextaddr_gray==sync_wr_
 Addr2_gray);
                                     Assign Asyn_full = (Wr_nextaddr_gray=={~sync_rd_addr2_gray[asize:asize-1],     SYNC_RD_ADDR2_GRAY[ASIZE-2:0]});//The highest 2-bit inversion; Gray code, the direct comparison between the two are exactly the same; Gray code is full, must meet the highest bit different, the second high is different, the rest of the same, to meet full conditions; so the highest 2 bits are flipped,
 The rest remains the same; @ (Posedge wr_clk) begin full <= asyn_full;
 End always @ (Posedge rd_clk) begin Empty <= Asyn_empty; End//////////////////////////////////////////////////////////////////////////////Endmodule

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