Asynchronous Reset synchronization release

In FPGA design, resetting is often encountered. Generally, resetting is divided into synchronous resetting and asynchronous resetting.

Compared with Synchronous Reset, Asynchronous Reset uses the clr end of the d Trigger, which consumes less hardware resources. In many cases, the reset mode of each module is selected as Asynchronous Reset. However, asynchronous signals are prone to potential risks: When the Asynchronous Reset signal cancels the reset state near the rising edge of the clock, the timing circuit may be faulty here.

One way to solve this problem is to pre-process the Asynchronous Reset signal to make it a form of Asynchronous Reset and synchronous release.

The circuit I designed is as follows:

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity Reset isport(    CLK:            in        std_logic;    RST_n_in:        in        std_logic;    RST_n_out:        buffer     std_logic);end Reset;architecture ex of Reset is    signal rst_clk_syn:        std_logic;begin    RST_n_out <= rst_clk_syn and RST_n_in;    process(CLK, RST_n_in)    begin        if(CLK‘event and CLK = ‘1‘) then            rst_clk_syn <= RST_n_in;        end if;    end process;end ex;

The RTL-level comprehensive results are as follows:

The simulation results are as follows:

After this structure, the Asynchronous Reset signal can be transmitted to other Asynchronous Reset modules to reduce the instability caused by the asynchronous signal.