Asynchronous memory interface and synchronous Storage

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Memory interface types can be divided:

Asynchronous memory interface and synchronous storage interface.
Asynchronous memory interface type is the most common and well-known. Generally, MCU

This type of interface is used. Corresponding memory: SRAM, Flash, NVRAM ...... And many other

Analog/digital I/O devices connected in parallel, such as A/D, D/A, and open-in/Open

Implemented in asynchronous memory interface form.
The synchronous storage interface is relatively unfamiliar. It is generally used in high-end microprocessor.

The c55x and C6000 series DSPs contain synchronous memory interfaces. Corresponding memory: Synchronous static

State memory: sbsram and zbtsram, synchronous dynamic memory: SDRAM, synchronous FIFO

. SDRAM may be the most well-known synchronization memory, which is widely used as the memory of PCs.

.
C2000, c3x, and C54X DSPs only provide asynchronous memory interfaces.

Memory direct interface. If you want to connect to the synchronous storage interface, you must add the corresponding memory control.

Generally, this is not the case from the consideration of circuit complexity and cost. C55x and C6000 series

DSP not only provides an asynchronous memory interface, but also a synchronous memory interface for its performance.

Asynchronous memory interfaces of c55x and C6000 series DSPs are mainly used to expand flash and analog/digital

I/O, Flash is mainly used for storageProgramAfter the system powers on, The Flash program is loaded to the DSP

In the internal or external high-speed RAM, this process is called the main

To be used to expand external high-speed data or program Ram, such as sbsram, zbtsram, or SDRAM

.
How to Design the external memory circuit of the DSP system, that is, how the DSP correctly matches various types

Memory chip interface. It is a difficult point in memory design. In addition, the DSP external memory circuit

The following problems are often encountered in the design:

1. The external memory interface signal provided by DSP and the interface signal required by the memory chip are incomplete.

As a result, some DSPs support access to multiple data widths, such as 8/16/32-Bit Data widths.

How to implement it in the circuit?

2. During PCB cabling, equivalent switches are often performed to facilitate cabling.

Some memory can be used for equivalent switching, but what is not?

Asynchronous memory: Flash

For flash, the read operation is the same as the SRAM operation, and the erasure and write operations are given in the form of command sequence

, Different vendors, the command sequence may be slightly different after writing the command sequence, flash automatically runs the corresponding

Operation, until the operation is completed, and then automatically changes to the read status. Read flash to obtain

Status information about whether the operation is completed, not the storage unit data.
For flash, because the erasure and write operations are given in the form of command sequences, you can program and Package

There are two methods:

1. Online, load2 program, set the program to be writtenCompositionWrite to flash.
2. offline data is written using JTAG.
There are four types of 3.3 V, 16-bit width, and industry-standard flash. Their pins are compatible, all of which are 48

TSOP encapsulation of pins. During PCB cabling, you can use a maximum of 1 MB x 16-bit flash for cabling.

Install any flash based on the capacity. The data line and address line of Flash cannot be equivalent exchange

. Considering bootloader, flash should be positioned in a special position, and the design should refer to the corresponding device's

Data Manual.
1. VC33, flash should be located at 1000 h of page0, or 400000 h of page1, or

The fff000h of page3, which can be 8/16/32-bit data width.
2. C54X series DSPs, flash should be located in the 8000h ~ data storage space ~ Ffffh, supporting

8/16-bit data width
3. c55x series DSPs, flash should be located at 200000 H of the CE1 storage space, and c5509 only supports

Supports 16-Bit Width while c5510 supports 8/16/32-bit data width.
4. c620x/c670x series DSPs, flash should be located in the CE1 storage space, with a size of 64 k characters

Section, supports 8/16/32-bit data width and can only be in the little endian format.
5. c621x/c671x series DSP, flash should be located in the CE1 storage space, the size is 1 KB

Supports 8/16/32-bit data width, either in little endian format or big

Endian format.
6. C64x series DSPs, flash should be located in the CE1 storage space of emifb, with a size of 1 KB

Only supports 8-bit data width, either in the little endian format or in the big endian format.

.

Commonly used flash: SST39VF400A-70-4C-EK, 256k x 16 bit, 3.3 V, 70ns.

SDRAM

SDRAM, that is, synchronous DRAM (synchronous dynamic random memory ),Once a PC

One of the most widely used memory types on computers, even today, SDRAM is still in the market

Have a place. Since it is "synchronous dynamic random memory", it indicates that its working speed is

System bus speed synchronization. The memory is divided into pc66, pc100, and pc133.

Specification, and the number next to the specification represents the maximum operating system bus speed of the memory,

For example, pc100 indicates that the memory can be synchronized in a computer with a system bus of MHz.

. Synchronization with the system bus speed, that is, synchronization with the system clock, so as to avoid unnecessary

Wait for a period to reduce the data storage time. Synchronization also allows the storage controller to know which Clock Pulse week

Therefore, data can be transmitted as soon as the pulse rises. 3.3 For SDRAM

Working voltage, pin dimm interface, bandwidth is 64-bit. SDRAM is not only applied in memory

Is also common in video memory.

SDRAM working process:
1. After the power-on is stable, after 8 refresh cycles, enter the mode register settings (MRS) to determine the core

Working Mode of slice, Cl, BL, burst transmission mode.
2. the row is valid, and both slice selection and bank selection are performed. CS Ras valid cas we none

Select the corresponding bank and line on the address line and Ba (in some documents, these two types are classified as addresses

Line, BA is the highest bit of the address ).
3. Column read/write. When the row is valid, select the expected column for read or write operations. CAS is valid and RAS is used.

Invalid. The online address is a column address. The we signal determines whether the operation is read or write.

Some important knowledge in SDRAM:
1. trcd, Ras to CAS delay, that is, when the row is valid, it cannot be in the next clock cycle

Read/write operations, but wait for a certain period of time, which is trcd, usually 2

Or three clock cycles.
2. CL: Read latency. When CAS arrive during the read process, data cannot be output to Io immediately.

On the bus, it takes a certain period of time, this time is cl, it is because the signal needs to pass through

Amplification and other processing results. The value can be changed in the MRS, in the unit of the chip clock cycle.
3. There is no latency in the write operation. After CAS sends data, it can send
4. You can use BL settings to continuously transmit a set of data without having to provide the corresponding address.

A data address is enough.
5. During the pre-charging process, you need to perform the pre-charging operation when selecting different lines of the same bank,

It generally has two clock cycles.
6. There are two types of refresh process: Automatic refresh and self-Refresh. Improve SDRAM Efficiency

We must minimize the data delay caused by the time mentioned above.

Different models aside,The biggest difference between synchronization and Asynchronization is that there is no cache on the hardware circuit, rather than

Storage is completed within the specified period.
Synchronization refers to writing data into the memory in sequence, and asynchronous refers to the time (or

When required) write to memory.
Asynchronous implementation of a circuit hardware. As you said, writing based on a fixed time period is not a clock period.

In addition, it is written when needed, and there is no time period.
For example, the personal computer North bridge connects to the CPU-memory, direct writing; cache write is required

Write time is required, while DRAM is written in a fixed sequence.