AT45DB041B Chinese data-AT45DB041 Chinese Data

AT45DB041B is 2.7-3.3 V 20 MHz

AT45DB041 is 4.5-5.5 V 10 MHz (discontinued)

AT45DB041 is a new flash chip of ATMEL. The chip has many advantages such as large capacity, fast read/write speed, and few peripheral circuits. More importantly, the chip can work at least 2.5 V, and the operating current is only 4mA, therefore, it has been widely used in mobile communication and portable applications.

 

Chip working principle and hardware connection

Data in AT45DB041 is stored by page. The primary storage has 2048 pages, with 264 bytes per page. Therefore, the total size is KB (about 4 MB ). Data stored in the primary storage will not be lost after power loss. In addition to primary storage, AT45DB041 also has two 264-byte data caches. The cache can be used as a buffer area for data exchange between the primary storage and the external storage, or temporary data can be saved. Cache reading and writing is convenient and fast, but data loss occurs when the power is down. AT45DB041 adopts the serial mode for Data Reading and writing, which is fast. The transmission time from page to cache is about 80 s, and is compatible with CMOS and TTL input and output.

AT45DB041 is enabled through the chip selection pin/cs, and reads and writes data through the serial output (so) and serial input (SI. Reads and writes are controlled by the serial clock (sck.
The running of the device is controlled by the instructions of the microprocessor. A valid command starts from the descent edge of the/CS pin and follows the corresponding 8-bit operation code and the specified cache or Master Address Code. When the/CS pin is low, the rotation clock pin (sck) controls the operation code and the specified cache or Master Address Code to load through the si Port. All commands, addresses, and data are transmitted starting from the high byte.

Data Reading

Read cache: You can choose to read one of the two caches using different operation codes (operation code 54h is used as read cache 1, and operation code 56h is used as read cache 2 ). In order to implement read cache operations, the 8-bit operation code must be followed by a 15-bit identifier code, 9-bit address code, and 8-bit identifier code. The 9-bit address code (BFA8-BFA0) is used to specify the first byte to be read. Under the control of the rotation clock sck, the operation code, address code, and any Italian Code are loaded from Si. After loading, the cached data can be read from so under the control of sck rotation clock. When the end of the cache is read, the device will continue to re-read from the beginning of the cache. /CS must be kept low throughout the process. After the read cache is complete, the read operation will be terminated when a low-to-high level jump on/CS.

Transmission from the primary storage page to the cache: one page of data can be transferred from the primary storage to the cache 1 or 2. 8-bit operation code (53h for cache 1, 55h for cache 2) followed by 4-bit reserved bits, 11-bit for specifying the destination Page address bits (PA10-PA0), and 9-bit any bits, load data from Si under the control of sck. In this process, the/CS pin must maintain a low potential. After loading, after detecting a low-to-high level hop on/CS, the data on the primary storage page is transmitted to the cache. During data transmission, status registers indicate that the status is busy.

Data Writing

Write cache: Under the Control of sck, 8 bits operation code (84h for cache 1, 87h for cache 2) followed by 15 bits meaning code and 9 BITs address code (BFA8-BFA0) it is loaded by Si, where the nine-bit address Code specifies the first byte written in the cache, and the data follows the address code input. /A low-to-high hop on CS will end the write cache operation.

Transfer of cache with built-in erasure to primary storage page: 8-bit operation code (83h for cache 1, 86h for cache 2) followed by 4-bit reserved, 11-bit specifies the address code (PA10-PA0) of the primary page to be written, and 9-bit Letter of Intent, loaded from Si under the control of the rotation clock sck. When a low-to-high hop is detected on/CS, the device first deletes the selected primary storage page and then writes the data stored in the cache to the page. The process of erasure and writing is automatic, and the process does not exceed 20 ms. During this time, the Status Register indicates that the status is busy. Read Status Register value: the read status register value can be used to determine the idle status of the device. The idle status is indicated by the Register's 7th bits. If 7th bits are 1, the device is idle and can receive the next command. If the value is 0, the device is busy. After loading the 8-bit operating code for 57h, you can read the value of the 1-byte Status Register from so.

Write protection (/WP) b041 only applies to the first 256 pages of the primary storage. When the/WP pin is low, flash prohibits write operations (read-only) on the first 256 pages of the primary storage, but other pages of the primary storage are not affected and can still be read and written. The selective write protection function of AT45DB041 provides great convenience for users. Users can save very important data, such as system parameters, passwords, and identity information, to the first 256 pages of the primary storage, set/WP to a lower level so that the data is in the write protection state to ensure that the data is not erased by mistake. At the same time, users can still read and write other addresses. If you leave the/WP pin unmoved or grounded, flash will not be able to write protection, and all the primary storage pages can be read and written.

Reset (/reset) b041 uses a low-level reset, that is, when the/reset pin has a low-level (<0.6 V), the chip stops working, after the level of the/reset pin is increased (> 2.0 V), the Operation resumes normal operation. In order to avoid the impact on the normal operation of the chip due to voltage instability during power-on, it is best to delay 10 ms after the system is started, and then perform flash operations.

Interface with microprocessor

The b041 peripheral circuit is very simple and can be easily connected to the microcontroller. So, Si, sck,/cs,/WP are connected to the general I/O of the microprocessor respectively.

Software Design

The following describes the Data Reading and Writing of AT45DB041.

AT45DB041 reads and writes data mainly including the operation code, Reserved Bit, address code, meaning code, user data loading, and user data and status word reading.

Data Loading subroutine

The data to be loaded (operation code, Reserved Bit, address code, letter of intent, and user data) is stored in the address unit starting from R0.
; Data Count in R6 dadain: Push ACC
CLR Cs; Enable R0
Trsmit: mov A, @ R0
MoV R7, #08 h 1 byte = 8 bits
Loopt: rlc a; the data to be sent is removed from high to low
CLR sck
MoV Si, which sends 1-bit data to Si
NOP
SETB sck; number of rising edges of sck at45dbo41 from Si
Djnz R7, loopt; One-byte data transmission is complete
INC R0
Djnz R6, trsmit
SETB Cs; all data has been sent
Pop ACC
RET

Data Reading Subroutine:

Store the Retrieved Data (user data and status words) in the address unit starting with r1

; Data Count in R6
Dataout: Push ACC
CLR,
CLR C
CLR Cs; Enable
Receive: CLR sck
MoV R7, #08 h
Loopr: SETB sck on the rising edge of sck AT45DB041 put the data on S0
MoV C, so; extract 1-Bit Data
NOP
SETB sck
RLC
Djnz R7, loopr; One-byte data received
MoV @ R1,
INC r1
Djnz R6, receive
Setb csp; all data has been received
Pop ACC
RET

 

Good information: http://tech.ddvip.com/2008/08/121861234853580_3.html