Aveon-mm____sd_card IP Design

(1) Code

/************************************ * *****************************
* Module name: crazy_sdcard
* Author: crazy bingo
* Device: ep2c8q208c8
* version: Quartus II 10.1
* Date: 2011-3-3
* description:
************************************* *******************************/

/*************************************** *****************************
* Module name: crazy_key_led
* Author: crazy bingo
* Device: ep2c8q208c8
* Version: Quartus II 10.1
* Date: 2011-3-2
* Description:
**************************************** *****************************/
Module crazy_sdcard
(
// Aveon clock
Input csi_clk,
Input csi_rst_n,
// Aveon-mm
Input avs_chipselect,
Input [1:0] avs_address, // multiple of 4
// Input [1:0] avs_byteenable_n, // 128
Input avs_write,
Input [31: 0] avs_writedata, // 32bit CPU
Input avs_read,
Output [31: 0] avs_readdata, // 32bit CPU
// Aveon conducting it
Output Reg coe_sd_cs,
Output Reg coe_sd_clk,
Input coe_sd_miso,
Output Reg coe_sd_mosi // 2 bis led
);

// Write
Reg [1:0] coe_led_data_r;
Always @ (posedge csi_clk or negedge csi_rst_n)
Begin
If (! Csi_rst_n)
Begin
Coe_sd_cs <= 0;
Coe_sd_clk <= 0;
Coe_sd_mosi <= 0;
End
Else if (avs_chipselect & avs_write)
Begin
Case (avs_address)
0: coe_sd_cs <= avs_writedata [0];
2: coe_sd_clk <= avs_writedata [0];
3: coe_sd_mosi <= avs_writedata [0];
Default:; // 4
Endcase
End
End

// Read
Reg avs_readdata_r;
Always @ (posedge csi_clk or negedge csi_rst_n)
Begin
If (! Csi_rst_n)
Avs_readdata_r <= 0;
Else if (avs_chipselect & avs_read & (avs_address = 4) // For steady state
Avs_readdata_r <= coe_sd_miso;
End
Assign avs_readdata = avs_readdata_r;

Endmodule