Basic FPGA development process

Source: Internet
Author: User
Tags xilinx ise

Typical FPGA development process and precautions

The FPGA design process is the process of developing FPGA Chips Using EDA development software and programming tools. Typical FPGA development processes generally include function definition/device selection, design input, function simulation, comprehensive optimization, integrated post-simulation, implementation, post-wiring simulation, board-level simulation, and chip programming and debugging..

1) function definition/device Selection

Before the FPGA design project starts, there must be a systematic definition of functions and division of modules. In addition, according to the task requirements, such as the functions and complexity of the system, weigh the working speed and the resource, cost, and wiring of the device, and select the appropriate design scheme and device type. Generally, the top-down design method is used to divide the system into several basic units, and then divide each basic unit into the basic units at the next level, until you can directly use the EDA component library.

2) design input

The design input refers to the process of expressing the designed system or circuit in some form as required by the software development and inputting it to the EDA tool. Common methods include hardware description language (HDL) and schematic input. Schematic input is the most direct description method, which is widely used in the early development of programmable chips. It draws a schematic diagram from the component library. Although this method is intuitive and easy to simulate, it is inefficient and difficult to maintain, making it difficult to construct and reuse modules. The main drawback is poor portability. After the chip is upgraded, all the schematics need to be modified.

At present, the most widely used in actual development is the HDL language input method. The text description design can be divided into common HDL and behavior HDL. Common HDL expressions include Abel and cur. It supports expressions such as logical equations, truth tables, and state machines, and is mainly used for simple small design. In medium and large projects, the main uses of behavior HDL, whose mainstream languages are OpenGL and VHDL. Both languages are standards of the American Institute of Electrical and Electronics Engineers (IEEE). Their common characteristics are: the language has nothing to do with the chip technology, which is conducive to top-down design, it facilitates the division and Transplantation of modules, provides good portability, strong logic description and simulation functions, and high input efficiency. In addition to the IEEE standard language, there are also manufacturers' own languages. You can also use the hybrid design method, supplemented by the principle diagram, to give full play to their respective characteristics.

3) functional simulation

Functional simulation, also known as the pre-simulation, verifies the Logic Functions of the circuit designed by the user before compilation. At this time, the simulation does not have delay information and only checks the preliminary functions. Before simulation, you must first use the waveform editor and HDL to create a waveform file and a test vector (that is, combine the input signal concerned into a sequence ), the simulation results generate a report file and the output signal waveform, from which you can observe the signal changes of each node. If an error is found, the design modification logic design is returned. Commonly used tools include Modelsim of model tech, VCs of sysnopsys, NC-Tilde of cadence, and NC-VHDL.

4) Comprehensive Optimization

The so-called synthesis is to convert the description of a higher abstraction level into a lower description. The logical connections generated based on the objectives and requirements are optimized comprehensively to make the hierarchical design flat for FPGA layout and wiring software. At the current level, integrated optimization (synthesis) refers to compiling design input into a logical connection network Table consisting of basic logical units such as gate, or gate, non-gate, ram, and trigger, it is not a real door-level circuit. Real and specific door-level circuits are generated based on the Integrated standard door-level structure network table by leveraging the layout and wiring functions of FPGA manufacturers.

In order to be converted to a standard portal-level structured network table, the compiling of the HDL program must conform to the style required by the specific synthesizer. Because the integration of the gate-level structure and RTL-level HDL program is a mature technology, all the integrators can support this level of synthesis. Common integrated tools include Synplify/Synplify Pro software from synplicity and integrated development tools released by FPGA manufacturers.

5) integrated post-Simulation

After integration, check whether the integrated results are consistent with the original design. During simulation, the standard delay file generated by the synthesis is reversed to the synthesis simulation model to estimate the impact of the door delay. However, this step cannot estimate the line latency. Therefore, there is still a certain gap with the actual situation after wiring, which is not very accurate. The current integrated tools are relatively mature and can omit this step for general design. However, if the circuit structure and design intent are found to be inconsistent after layout and wiring, you need to go back to the integrated simulation to confirm the problem. The software tools introduced in functional simulation generally support integrated post-simulation.

Typical FPGA design process structure

6) Implementation and Layout

Layout and wiring can be understood as using the implementation tool to map logic to the resources of the target device structure, determine the optimal logic layout, and select the wiring channel connecting the logic and the input and output functions, and generate relevant files (such as configuration files and related reports). The logical network table generated in a comprehensive manner is configured on a specific FPGA chip. layout and wiring are the most important process. The layout reasonably configures the hardware primitives and underlying units in the logical network table to the internal hardware structure of the chip, and usually needs to make a choice between the optimum speed and the optimum area. Based on the topological structure of the layout, the cabling properly and correctly connects various components using various connected Resources in the chip.

At present, the FPGA structure is very complex, especially when there are timing constraints, you need to use the timing-driven engine for layout and wiring. After the wiring is completed, the software tool automatically generates a report to provide the usage of each part of the resources in the design. As only FPGA chip manufacturers have the best understanding of the chip structure, the layout and wiring must be the tool provided by chip developers.

7) timing simulation

Time series simulation, also known as post-simulation, refers to labeling the delay information of the layout and wiring to the design network table to detect whether there are any time series violations (that is, it does not meet the time series constraints or the inherent time series Rules of the device, such as creation time and retention time. Timing simulation provides the most comprehensive and accurate latency information, which can better reflect the actual operating conditions of the chip. Because the internal latency of different chips is different, different layout schemes also have different effects on the latency. Therefore, after layout and wiring, it is necessary to conduct timing simulation on the system and each module, analyze the timing relationship, estimate the system performance, and check and eliminate the risk of competition. The software tools introduced in functional simulation generally support integrated post-simulation.

8) board-level simulation and Verification

Board-level simulation is mainly used in high-speed circuit design. It analyzes signal integrity, electromagnetic interference, and other features of high-speed systems. It is generally simulated and verified by a third-party tool.

9) chip programming and debugging

The last step of the design is chip programming and debugging. Chip programming refers to the generation and use of data files (BIT data stream files, bitstream generation), and then download the program data to the FPGA chip. Chip programming must meet certain conditions, such as programming voltage, programming time series, and programming algorithms. Logic Analyzer (LA) is the main debugging tool designed for FPGA. However, it requires a large number of test pins and La is expensive.

Currently, mainstream FPGA chip manufacturers have provided embedded online logic analyzers (such as chipscope in Xilinx ISE, signaltapii in Altera quartuⅱ, and signalprob) to solve these contradictions, they only need to occupy a small amount of logical resources on the chip and have high practical value.

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