Basic knowledge of operating UCOS on S3C2410-knowledge of arm9-chip related to operating uCOS-continued

User Mode (user mode): the normal mode of running the application;

Fast interrupt mode (FIQ mode), used to support data transmission or channel processing;

Interrupt mode (IRQ mode), used for normal interrupt processing.

Super User Mode (SVC mode), operating system protection mode

Exception interrupt mode (ABT mode). Enter the data and log on to or prefetch the exception interrupt command.

System Mode (sys mode) is a privileged user mode used by the operating system.

Undefined mode (und mode). This mode is used when undefined commands are executed.

 

External interruptions, abnormal operations, or software control can change the interrupt mode. Most applications run in user mode. The privileged mode is used to protect resource services by handling interrupted or abnormal requests or operations.

 

These operating modes are different environments where the chip hardware provides programs to run. Different modes have different hardware access permissions and use different registers. This provides different permission mechanisms for different programs. For example, if your operating system code runs in a mode with high permissions, your application is running in a low-Permission mode. This protects operating system code.

Registers, visible registers in each mode, and functions of each register:

Arm has 37 32-bit registers, 31 of which are General registers and 6 are status registers. But at the same time,

Not all registers are visible to programmers. Whether the memory is visible (accessible) at a certain time.

The current working status and working mode of the scheduler. Register 1 in each mode:

The system mode and user mode use the same register. Registers that draw triangular shadows indicate that in different modes

There are different physical registers.

The following describes the categories:

General registers

General registers of arm include R0 ~ R15, where r0 ~ R7 is an ungrouped register, and the same sending is used in each mode.

Memory. R8 ~ R14 has an independent physical register in FIQ mode, which aims to accelerate the interrupt response speed from the hardware.

Save the program execution site. The two registers R13 and R14 have their own independent registers in each mode. R15 only

One, all modes are public.

The following describes the special functions of these registers:

Register R13: In arm commands, R13 is often used as a stack pointer. Each running mode has its own independent stack, which is used to save the program running environment when the interruption occurs and process control when the C language is executed.

Register R14: the address of the return point. The system executes a "Jump and link" (BL) command.

R14 receives a copy of R15. In other cases, it can be used as a general register. Corresponding to it

In other modes, the Private Registers r14_svc, r14_irq, r14_fiq, r14_abt, and r14_und are also used for protection.

The return value of R15 when the BL command is executed in the interrupted or abnormal circumstances.

Register R15 is a program counter (PC ). In the arm state, the bits [1:0] of R15 is 0, and bits [31: 2] saves the PC

. In the thumb state, BITs [0] is 0 and bits [31: 1] saves the Pc value.

FIQ mode has 7 private register R8-14 (R8_fiq-R14_fiq ). In arm State, most FIQ processes do not need to store any registers. User, interrupt, and exception abort. Both superuser and undefined mode have two private registers, R13 and R14. Each of these modes can have a private Stack pointer and link register.

Program Status Register

ARM920T has one current Program Status Register (CPSR), and five other program State registers (spsrs) for exception interrupt processing. The functions of these registers include:

Keep the information about the recently completed ALU operation;

Control the enabling and disabling of interruptions;

Set the operating mode of the processor.

 

2 shows the bit definition of the program status register:

 

For more information about the meanings of these bits, see datasheet.

Exception:

When a normal program execution process is temporarily stopped for some reason, it is called an exception. For example, if the chip obtains an Unknown command, when the command is executed, the abort exception is aborted and enters the abort mode. That is to say, an exception will occur when the exception is not met, and different exceptions will lead the processor to different processing modes.

You want to know when and how an exception occurs? What do chips do after they happen? How to return from these exceptions? What is an abnormal vector table? Then read the chapter 2 Program's model of datasheet carefully. This chapter describes and explains these problems in detail.

Of course, these are related to the subsequent UCOS. For example, UCOS and user applications are uniformly compiled and all run in SVC mode. When an external interruption occurs, the system switches to the interrupt mode.

See the following exception (Interruption) vector table:

Address	Exception interrupt type	Enter the Time Processor Mode
Zero X 00000000	Reset	Supervisor
Zero X 00000004	Undefined instruction	Undefined
Zero X 00000008	Software interrupt	Supervisor
0x0000000c	Abort (prefetch)	Abort
Zero X 00000010	Abort (data)	Abort
Zero X 00000014	Reserved	Reserved
Zero X 00000018	IRQ	IRQ
0x0000001c	FIQ	FIQ

 

The abnormal vector table is a completed jump instruction table. The interrupt vector table is located at the beginning of 0 of the memory address. When an exception occurs, the CPU finally needs to change the Pc value to the jump command in the vector table to implement the jump to execute the corresponding service program. Of course, the CPU running mode is changed. We can see that the IRQ interrupt is abnormal. This address vector is the entry address of the External Interrupt. We know that there are many interrupt sources supported on the arm9-chip, And the interrupt entry is one, how to identify the specific interrupt source. This part of knowledge is the content of the interrupt controller. Please participate in the following article or in chapter 14 of datasheet interrupt controller.

For more details, see Datasheet of 920t !!!!!

For details about the arm Interrupt System, see ARM920T Interrupt System. The uCOS-related ARM chip knowledge is over. Of course, there are still a lot of ARM chip knowledge. Please refer to Datasheet of 920t !!!!!