[Basic knowledge]s3c2416x clock configuration detailed steps

Introduction

List several registers to use first: LOCKCON0 LOCKCON1 oscset mpllcon epllcon epllcon_k

These 6 registers control 2 internal PLL phase-locked loops, an external crystal oscillator. The output values of these two independent PLL phase-locked loops are determined by the setting values of Mpllcon and Epllcon , respectively. The stable output time of the PLL is determined by LOCKCON0 and LOCKCON1 . The stability time of the crystal oscillator is determined by Oscset .

Normally, the PLL is again opened, back to the system to provide output to each module, but before the stable output, there will be some small jitter output, in order to filter these jitter output, you need to delay a period of time after the PLL is opened, and then output the clock to each module, The delay value set here is LOCKCON0 and LOCKCON1, which set the delay value before the stable output of MPLL and EPLL respectively. Typically, the delay is at least greater than 300US.

And the crystal oscillator to stabilize the time to follow the manual recommended values set. 1. First set the phase-locked loop output, including Mpllcon, Epllcon 1.1 Configuring the master clock Mpllcon

According to the recommended values set in the data sheet, set the MDiv to 400,pdiv set to 3,sdiv set to 1, so that the Mpllcon value =0x00640061, that is, the PLL output is 800MHZ. Because the next use MPLL, so the output of the MPLL is turned on.

0000 0000 0110 0100 0000 0000 0110 0001
That is, Mpllcon = 0x00640061 1.2 Configures the secondary clock Epllcon

According to the recommended values set in the data sheet, set the MDiv to 32,pdiv set to 1,sdiv set to 2, so that the Mpllcon value =0x01200102, that is, the EPLL output is 96MHZ
Because it is not available, the output of EPLL is turned off in Bootstrap.bin.

0000 0001 0010 0000 0000 0001 0000 0010
That is, the Epllcon = 0x01200102 1.3 Configures the stable output buffer delay time value of the master clock

LOCKCON0 = 0x0000ffff 1.4 Configure a stable output buffer delay time value for the secondary clock

LOCKCON1 = 0x0000ffff 2. Configure each module clock, including ARMCLK, HCLK, PCLK, SCLK

After the output of the PLL is set, then the clock value of each module is set, the PLL is only stable output, and as for each module, we need to set the divider and the value of the divider for each module separately. CLKSRC CLKDIV0 CLKDIV1 CLKDIV2 hclkcon pclkcon sclkcon 2.1 Set CLKSRC, select Clock Source

0000 0000 0000 0000 0000 0001 0101 1000
That is, CLKSRC = 0x00000157 2.2 Sets the CLKDIV0, which sets the value of the Prescaler factor for the MPLL of each module clock

0000 0000 0000 0000 0000 0010 0010 1101
That is, clkdiv0=0x0000022d

This setting, based on the output of the Mpll=800mhz, gets the Armclk=400mhz,hclk=133mhz pclk=66mhz 2.3 setting CLKDIV1, which sets the value of the prescaler coefficients of each module clock EPLL

0000 0000 0000 0000 0000 0000 0000 0000
That is, clkdiv1=0x00000000 2.3 Sets the CLKDIV2, which sets the value of the Prescaler factor for each module clock HSMMC

0000 0000 0000 0000 0000 0000 0000 0000
That is, clkdiv2=0x00000000 2.4 Sets the Hclkcon, which corresponds to the clock enabled by the peripherals used

Depending on what you use to make it, the default is to

1111 1111 1111 1111 1111 1111 1111
That is, HCLKCON=0XFFFFFFFF 2.4 Sets the Pclkcon, which corresponds to the clock enabled by the peripherals used

1111 1111 1111 1111 1111 1111 1111
That is, PCLKCON=0XFFFFFFFF 2.4 Sets the Sclkcon, which corresponds to the clock enabled by the peripherals used

1111 1111 1111 1101 1111 1111 1111
That is, Sclkcon=0xffffdfff 3. Do not bother to look at the process, directly see the results put here

Mpllcon = 0x00640061
Epllcon = 0x01200102
LOCKCON0 = 0x0000ffff
LOCKCON1 = 0x0000ffff
CLKSRC = 0x00000157
clkdiv0=0x0000022d
clkdiv1=0x00000000
clkdiv2=0x00000000
Hclkcon=0xffffffff
Pclkcon=0xffffffff
Sclkcon=0xffffdfff

The result of the configuration above is to set the ARMCLK to 400mhz,hclk=133mhz,pclk=66mhz all the peripherals.