Build a low-cost, highly configurable bridging solution: Use d-phy-based MIPI standard peripherals in embedded designs

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The designers of embedded systems are facing a dilemma. On the one hand they need to reduce system costs. On the other hand, their system is facing the use of relatively narrow, small batch of applications, can not play a large-scale production efficiency. The high-volume consumer applications market provides components that can handle similar tasks and are less costly, but embedded system designers are unable to take advantage of these components because their system reliability is built on those traditional interfaces optimized for the embedded environment. This problem is most prominent in the display, camera and application processor, the low-cost, MIPI standard element for mobile platforms using an interface based on the d-phy physical bus, unable to communicate with the embedded system processor, because the latter is connected to the display via LVDS, RGB or SPI interface, and connecting the image sensor via a digital parallel interface, SUBLVDS or HISPI interface.

This article focuses on possible solutions to this problem and explores how embedded system designers can leverage the cost-effective components that system designers have already used in large-volume consumer electronics markets. This paper focuses on a new ultra-low density (ULD) FPGA and related reference design how to create a low-cost, highly configurable bridging solution that uses d-phy-based MIPI standard peripherals in embedded designs to open New horizons for emerging applications using MIPI-standard components.

Historical experience

Twenty or thirty ago when embedded system designers wanted to cut costs, they used the cost-effective platform of that era. By adopting standard hardware and software developed for the popular PC architecture, embedded system designers have achieved high reliability components validated by tens of millions of consumer electronics applications while reducing costs. Components and subsystems with peripheral Part interconnect standard (PCI) buses provide a very attractive and low-cost alternative to complex, expensive embedded bus architectures such as VME, STD, and Multibus. PCI and later PCIe buses enable embedded developers to take advantage of existing, easy-to-use design tools and open-source operating systems based on well-known architectures. This strategy brings many benefits, allowing designers to deliver low cost to end consumers, shorten development cycles, and make it easier to meet time windows for product launches.

The PC era has gone. The original PC architecture is no longer the best choice for a cost-effective architecture (Figure 1), and is replaced by today's mobile computing era. Now, if embedded system developers want to reduce system costs, they have to use the components and interfaces of today's fast-growing, high-volume smartphone and tablet market.

Figure 1 : Mobile devices are becoming the primary computing platform, bringing more types of applications, better user experiences, and faster networks.

Interface parameters for mobile and mobile related products

The majority of smartphones and tablets on the market now use buses and interfaces defined by the mobile Industry Processor Interface (MIPI) alliance. Established in 2003, the MIPI Alliance promotes the development of inter-component interconnection by developing technical specifications for a wide range of mobile system peripherals, such as sensors, memory, displays, RF components, and standard hardware and software interfaces between devices and application processors on other mobile platforms. Figure 2 shows a typical mobile platform MIPI standard interface.

Displays, cameras, and application processors may be the MIPI standard components that embedded system designers can benefit most from the mobile market. As shown in 2, today's mobile system design often includes an LCD display using the Display serial Interface (DSI) and a camera image sensor with a camera serial interface (CSI-2). The main challenge for embedded system designers is to build bridges between the mature interfaces commonly used in embedded applications and the interfaces defined by the MIPI Alliance in Mobile systems to take advantage of these lower-cost mobile application components. For example, in the embedded systems market, displays typically use LVDS, RGB, or SPI interfaces, and image sensors tend to use digital parallel interfaces, SUBLVDS, or HISPI interfaces. Most embedded processors do not provide a DSI display interface. This shows that designers need to bridge the embedded processor with the DSI display. Similarly, embedded system design teams need to bridge the CSI-2 interface if they want to integrate low-cost image sensors for the mobile application market.

Figure 2 : by MIPI the mobile platform interface defined by the Federation.

d-phy Interface

The MIPI CSI-2 and DSI interfaces are based on the physical layer bus protocol named D-phy. The d-phy uses a differential clock and 1-4 pairs of differential data lines to transmit data, and the D-phy is a center-aligned source synchronization interface with data transfer at the upper and lower edges of the clock. One device acts as the transmitter, and the other device acts as the receiving end. The bus can convert the differential signal into a single-ended signal during operation. Typically differential or high-speed (HS) mode is used for high-performance video transmission, while the single-ended low-power (LP) mode is used to transmit control data.

The DSI HS interface is operating with the same electrical characteristics as an adjustable low voltage signal (SLVS) standard device at 200mV common-mode voltage. A DDR source synchronous clock and 1-4 interface data channels are used. The higher the display resolution and refresh rate requirements, the more data channels and higher rates are required. The DSI interface uses LP mode on data channel 0 to configure register mappings for the display. This mapping is known as the display instruction set (DCS). Therefore, when building DSi interface bridging, designers not only need to map video or image data to HS mode, but also a set of mechanisms for configuring the display in LP mode. Please note that this is the key difference between the DSi and CSI-2 interfaces. The CSI-2 image sensor uses an independent i²c-bus to program the image sensor rather than the LP mode.

Today's application processors offer compelling features, high integration, and low power consumption, and many embedded system designers cannot stop using their original processors due to their huge investment in the software and peripheral capabilities of the original processor. Software development costs for transitioning to another processor are often too high.

However, designers can still use the low-cost components used in some mobile products. For example, given that a large amount of investment in software is not recoverable, it is not difficult to imagine that the cost of transitioning a microcontroller-based embedded design to a new application processor is too high to be realized. Assume that an existing controller is connected to an LCD display using a CMOS RGB or LVDS Flatlink bus. The designers wanted to replace the LCD display with a low-cost DSI display, but the idea was not working because the DSI display was using a d-phy bus that was not compatible with the existing interface of the microcontroller (see Figure 3).

Figure 3 : Many traditional microcontrollers in the embedded market do not offer compatible MIPI the standard interface.

New Bridging options

Not long ago, embedded designers had to apply low-cost DSI displays to their designs using a dedicated ASIC with relatively high costs. In most cases, the cost of the ASIC is too high and the development cycle is too long to support such design changes. So the embedded designers had to continue to use more expensive displays.

Now, embedded designers can build d-phy bridges using solutions based on highly configurable, ultra-low-density FPGAs. For example, lattice semiconductors has developed a range of reference designs to help OEMs take advantage of the low cost benefits of MIPI cameras, application processors, and display components. Lattice has recently introduced 4 reference designs for MIPI camera and display applications: For DSI displays, MIPI DSI transmit bridging to the DSI receiver, and the application processor to the DSI receive bridging for displays not designed for mobile applications ; Connect the application processor to the CSI-2 of the non-CSI-2 image sensor to send the bridge, and connect the CSI-2 image sensor to the CSI-2 receive Bridge of the embedded ISP. With lattice uld FPGAs, embedded designers can quickly develop programmable bridging solutions that can be adapted to meet different requirements.

based on ultra-low density FPGA Bridging Solutions

Let's revisit the design of an embedded microcontroller using a CMOS RGB or LVDS Flatlink bus to connect the LCD display. Assuming that the microcontroller has a CMOS RGB888 (24-bit color bus) display interface, the first step is to determine how to program the configuration register of the DSI display. Typically, the microcontroller is configured with an i²c-bus. However, the I²c-Bus is unable to configure the MIPI DSI interface parameters for the display. DSI operates on the display instruction set (DCS) using the serial data channel in low-power mode. In this case, the FPGA bridge must convert the i²c instruction from the microcontroller into a series of DCS instructions to configure the DSI display. After the display configuration is complete, the FPGA needs to be set up to receive data from the RGB888 interface. If the resolution shown on the bus and the display is exactly the same, the FPGA converts the parallel bus into a serial DSi bus. If the resolution is inconsistent, the FPGA will scale the image. In these cases, you need to configure the output data channel for the DSI interface. Once the above steps are completed, the FPGA can output the DSI transmit interface to drive the DSI display.

What if embedded system designers want to integrate low-cost CSI-2 image sensors in their designs, but the image signal processor (ISP) in this design only has a CMOS interface? As mentioned before, the key difference between DSi and CSI-2 interfaces is how to map the data of an image sensor register. The CSI-2 uses an independent i²c-bus to accomplish this task. This distinction simplifies the task of designers by sending the register configuration of the image sensor directly to the ISP via the I²c-bus. In this scenario, the CSI-2 image sensor data is used as the input bus for bridging the FPGA, and the FPGA drives the CMOS parallel bus on the ISP (see Figure 4).

Figure 4 : Based on ULD FPGA of the CSI-2 image sensor bridging.

The same CSI-2 bridging solution can be used to extend the functionality of existing embedded systems. More and more applications require multiple image sensors, from 3D stereo audio to driving recorder. However, while mainstream ISPs commonly used on the market today have only one image sensor port, their performance is sufficient to support two sensors.

Using the two-sensor bridging described below (see Figure 5), embedded designers can extend the ISP port configuration to support more new applications. This example depicts an image sensor bridge for a driving recorder: two cameras, one pointing to the front windshield and the other to the driver. The bridge is connected to the parallel CMOS bus of each image sensor and is capable of outputting two combined 720P images in either the up/down, left/right configuration. This example is implemented using the lattice 1300 LUT MachXO3 FPGA, which enables synchronization and management of two image sensors. It outputs data in the CSI-2 format that the ISP or application processor can receive.

Figure 5 : Dual sensor bridging expands existing system functionality.

Conclusion

Developers in many applications want to minimize the cost of the system without sacrificing reliability, minimizing the size and power consumption. The embedded system market is no exception. Similar to the 90 's PC market, today's fast-growing MIPI interface smartphone and tablet market offers embedded designers an excellent opportunity to integrate a variety of lower-cost and proven components into the board as long as they address compatibility issues. With a new generation of programmable bridging solutions based on the Uld FPGA, embedded designers are now able to overcome these hurdles by leveraging the benefits of MIPI displays, image sensors, and application processors to reduce system costs and enhance reliability while satisfying the performance and real-time requirements of embedded systems.

About the author

Mr. Ted Marena is Director of business development at Lattice Semiconductor's chief technology Officer office. Mr. Marena has joined lattice since 1991 and has defined platform solutions for many vertical markets for consumer electronics, small wireless cellular networks, CMOS image sensors, displays, and automotive applications.

Prior to joining Lattice Semiconductor, Mr. Marena was a hardware design engineer at Wang Computers, where he designed Ethernet, ISDN, RS232 and t1/e1 boards. Mr. Marena holds a Bachelor of Science degree in electrical engineering from the University of Connecticut (University of Connecticut) and the Soundcraft Business School of Bentley College B Elkin McCallum Master of Marketing, School of Business)

Build a low-cost, highly configurable bridging solution: Use d-phy-based MIPI standard peripherals in embedded designs