Build time and keep time __FPGA

The clock is the most important and special signal of the whole circuit, most of the devices in the system are the movements of the clock on the jump along, which requires the clock signal Shiyancha is very small, otherwise it may result in sequential logic state error, so clear the FPGA design to determine the system clock factors, as far as possible the delay of the clock to ensure the design Stability has a very important meaning.

　　1.1 Establishment time and retention time

The time to build (tsu:set up times) is the time it takes to stabilize the data before the clock comes along, if the established time does not meet the requirements then the data will not be able to rise along the stable into the trigger in this clock; th:hold time is the time to keep the data stable. , the data also cannot be stabilized into triggers if the time is not enough to keep up with the requirements. The simple schematic diagram for establishing and holding time is shown in Figure 1 below.

Fig. 1 schematic diagram of retention time and establishment time

In the same module of FPGA design, it is often composed of combinational logic and sequential logic, so it is very important to establish a clear concept for establishing time and keeping time in order to ensure that data can be treated stably at the interface of these logic. The following questions are considered in the concept of establishing time and keeping time.

Fig. 2 A basic model in synchronous design

Figure 2 is a basic model for the unified design of a clock synchronization. The TCO is the delay of the data output of the trigger, the tdelay is the delay of the combinational logic, the Tsetup is the setting time of the trigger, and the TPD is the clock delay. If the first trigger D1 the maximum of T1max, the smallest is t1min, the maximum delay of combinatorial logic is t2max and the minimum is t2min. Ask the second trigger D2 time T3 and hold time T4 should meet what conditions, or know T3 and T4 so can allow the maximum clock period is how much. This problem is a problem that must be considered in the design, only if the problem is clarified can the design of the combinatorial logic delay meet the requirements.

The following sequence diagram is used to analyze: the input of the first trigger is D1, the output is Q1, the second trigger is D2 and the output is Q2;

The clock is uniformly sampled on the rising edge, in order to facilitate the analysis we discuss two kinds of situation namely first: assumes the clock delay TPD is zero, actually this kind of situation in the FPGA design is often satisfies, because in the FPGA design generally is uses the unified system clock, namely uses from the global clock tube foot input clock, This delay in the internal clock can be completely negligible. This case does not have to consider holding time, because each data is to maintain a clock beat and the delay of the line, which is based on clock delay is much less than the data delay based on, so to maintain time can meet the requirements, the focus is to care about the establishment of time, At this point the timeline diagram should be as shown in Figure 3 if the D2 is set to meet the requirements.

As you can see from the diagram, if:

T-tco-tdelay>t3

namely: tdelay< T-TCO-T3

Then it satisfies the requirement of establishing time, in which T is the cycle of the clock, in which case the second trigger can stabilize the D2 on the rise of the second clock, as shown in Figure 3.

Fig. 3 sequence diagram conforming to the requirements

If the delay of the combinatorial logic is too large,

T-tco-tdelay

Then the request will not be met, and the second trigger will pick up an indeterminate state on the rising edge of the second clock, as shown in Figure 4. Then the circuit will not work properly.

Fig. 4 The delayed time series of combinatorial logic does not meet the requirements

So that you can launch

T-tco-t2max>=t3

This is the time required for D2 to be established.

It can also be seen from the sequence diagram above that the establishment and retention time of the D2 is not related to the D1 and the time of maintenance, but only the combination logic of D2 and the delay of the D1 data transmission, which is also a very important conclusion. It shows that the delay has no superposition effect.

In the second case, if there is a delay in the clock, consider holding time in this case, and consider the time to build. The clock has a large delay is the use of asynchronous clock design method, this method is difficult to ensure the synchronization of data, so the actual design is rarely used. In this case, the output timing is as shown in Figure 5 if both the build time and the retention time meet the requirements.

Figure 5: There is a delay but satisfies the timing

It is easy to see from Figure 5 that the establishment time relaxed TPD, so the establishment of D2 time to meet the requirements:

Tpd+t-tco-t2max>=t3

Due to the establishment of time and the retention of time and is a stable clock cycle, if the clock has a delay, and the data delay is also smaller then the establishment of time is bound to increase, the retention time will be reduced, if the reduction to meet the D2 to maintain time requirements can not collect the correct data, as shown in Figure 6.

Then T (tpd-tco-t2min)

T (tpd+t-tco-t2min) >=t4 that TCO+T2MIN-TPD>=T4

From the above can also be seen if the tpd=0 is the clock delay of 0 Then the same is required tco+t2min>t4, but in the actual application due to the T2 delay is far greater than the delay of the trigger time that is T4 so unnecessary relationship to maintain time.

Figure 6: There is a delay and the retention time does not meet the requirements

To sum up, if you do not consider the clock delay so just care about the establishment of time, if the clock to consider the delay so more care to maintain time. The following will analyze how to improve the working clock in the synchronization system in the FPGA design.

　　1.2 How to improve the working clock in the synchronization system

From the above analysis can be seen in the synchronization system when the D2 to establish time T3 requirements for:

T-tco-t2max>=t3

So it is easy to launch the T>=t3+tco+t2max, where T3 for the D2 time tset,t2 for the combinational logic of the delay. In a design T3 and TCO are determined by the device fixed value, controllable also only T2 also when the input of the combination of logic delay, so by minimizing the T2 can improve the system's working clock. In order to achieve the reduction of T2 in the design can be achieved by the following different methods of synthesis.

　　1.2.1 to reduce delay by changing the way the line goes

Take the Altera device as an example, we can see a lot of floorplan in the timing closure She in Quartus, we can divide the She by row and by column, each bar represents 1 lab, 8 in each lab or 10 le. The relationship of their line-delay is as follows: the same lab (fastest) < the same column or peer < different rows and different columns. We're going to put a proper constraint on the complex. Generally add 5% margin is more appropriate, such as the circuit work in 100Mhz, then add constraints to 105Mhz on it, too large constraint effect is not good, and greatly increase the overall time) can be related to the logic in the wiring as far as possible cloth closer to the point, Thus reducing the delay of the line.

　　1.2.2 to reduce delay by splitting the combinatorial logic

As the general synchronization circuit is more than one lock (Figure 8), and to make the circuit stable work, the clock cycle must meet the maximum delay, shorten the longest delay path, can improve the circuit working frequency. As shown in Figure 7: We can decompose the larger combinational logic into smaller chunks, inserting triggers in the middle, which improves the frequency of the circuit. This is also the basic principle of the so-called "pipelining" (pipelining) technology.

For the upper part of Fig. 8, its clock frequency is constrained by the delay of the second large combinational logic, and the combined logic is distributed evenly by the appropriate method, which can avoid the excessive delay between the two triggers and eliminate the speed bottleneck.

Figure 7 Split Combinatorial logic

Figure 8 Transition Combination Logic

Then how to split the combinatorial logic in the design, the better way to accumulate in practice, but some good design ideas and methods also need to master. We know that most of the FPGA is based on 4 input lut, if an output corresponding to the judgment conditions greater than four input will be completed by a number of LUT cascade, so that the introduction of a combination of logic delay, we want to reduce the combination of logic, nothing more than to enter the conditions as little as possible, In this way, fewer lut can be cascaded, thus reducing the delay caused by combinatorial logic.

The flow of water that we normally hear is a way to improve the working frequency by cutting the large combination logic (in which the first or multilevel D triggers are inserted, thereby reducing the combination logic between registers and registers). Like a 32-bit counter, the counter's carry chain is very long, will inevitably reduce the working frequency, we can divide it into 4-bit and 8-bit count, whenever 4-bit counter to 15 trigger a 8-bit counter, so that the counter cut, but also improve the working frequency.

In the state machine, it is generally necessary to move the large counter to the state machine, because the counter this thing is usually more than 4 input, if again and other conditions as the state of the jump criterion, will inevitably increase the cascade of LUT, thus increasing the combinatorial logic. Take a 6-input counter as an example, we had hoped that when the counter to 111100 after the state jump, now we put the counter outside the state machine, when the counter to 111011 after the production of a enable signal to trigger the state jump, so that the combination of logic reduced. The state machine typically contains three modules, an output module, a module that determines what the next state is, and a module that saves the current state. The logic used to make up three modules is also different. Output modules usually contain both combinatorial logic and sequential logic, and the module that determines what the next state is usually composed of logical composition; The relationship of the three modules is shown in Figure 9 below.

Fig. 9 Composition of the state machine

The state machine is divided into three parts according to these three modules in all normal state machines, as follows is a good state machine design method:
/*-----------------------------------------------------
This are FSM demo program
Design Name:arbiter
File NAME:ARBITER2.V
-----------------------------------------------------*/
Module Arbiter2 (
Clock,//clock
Reset,//Active high, SYN reset
REQ_0,//Request 0
Req_1,//Request 1
GNT_0,
gnt_1);
-------------Input Ports-----------------------------
Input clock;
Input Res

ET;
Input req_0;
Input req_1;
-------------Output Ports----------------------------
Output gnt_0;
Output gnt_1;
-------------Input ports Data Type-------------------
Wire clock;
Wire reset;
Wire req_0;
Wire req_1;
-------------Output Ports Data Type------------------
Reg GNT_0;
Reg Gnt_1;
-------------Internal Constants--------------------------
Parameter SIZE = 3;
Parameter IDLE = 3 ' b001,
GNT0 = 3 ' b010,
GNT1 = 3 ' b100;
-------------Internal Variables---------------------------
reg [size-1:0] state;//SEQ part of the FSM
Wire [size-1:0] next_state;/Combo part of FSM
----------Code startes here------------------------
Assign next_state = Fsm_function (Req_0, req_1);
function [size-1:0] fsm_function;
Input req_0;
Input req_1;
Case (state)
Idle:if (req_0 = 1 ' B1)
Fsm_function = GNT0;
else if (req_1 = 1 ' B1)
Fsm_function= GNT1;
Else
Fsm_function = IDLE;
Gnt0:if (req_0 = 1 ' B1)
Fsm_function = GNT0;
Else
Fsm_function = IDLE;
Gnt1:if (req_1 = 1 ' B1)
Fsm_function = GNT1;
Else
Fsm_function =idle;
Default:fsm_function = IDLE;
Endcase
Endfunction
always@ (Posedge clock)
Begin
if (reset = = 1 ' B1)
State <=IDLE;
Else
State <=next_state;
End
----------Output Logic-----------------------------
Always @ (Posedge clock)
Begin
if (reset = = 1 ' B1) begin
Gnt_0 <= #1 1 ' b0;
Gnt_1 <= #1 1 ' b0;
End
ELSE begin
Case (state)
Idle:begin
Gnt_0 <= #1 1 ' b0;
Gnt_1 <= #1 1 ' b0;
End
Gnt0:begin
Gnt_0 <= #1 1 ' B1;
Gnt_1 <= #1 1 ' b0;
End
Gnt1:begin
Gnt_0 <= #1 1 ' b0;
Gnt_1 <= #1 1 ' B1;
End
Default:begin
Gnt_0 <= #1 1 ' b0;
Gnt_1 <= #1 1 ' b0;
End
Endcase
End
End to block Output_
Endmodule

State machines are usually written in 3-segment form, thus avoiding too large a combination of logic.

It's all about cutting combinatorial logic through the flow of water, but in some cases it's hard to cut the combinatorial logic, so what do we do in these situations?

The

State machine is such an example that we cannot add water to the state decoding combinatorial logic. If we have a state machine with dozens of states in our design, its state decoding logic will be very large, and there is no doubt that this is probably the key path in design. So what do we do? or old ideas, reduce combinatorial logic. We can analyze the output of the state, they are reclassified and based on this redefinition into a group of small state machines, through the selection of input (case statement) and to trigger the corresponding small state machine, so as to achieve the large state machine cut into a small state machine. In the specification of the ATA6 (the standard of the hard disk), there are about 200 commands to enter, and each command corresponds to many states, and if you do it with a large state machine (state set state) It is inconceivable that we can decode the command through the case statement and trigger the corresponding state machine. The frequency of this module can run higher.