Bus Operation Sequence and Operation Method

Bus Operation Sequence and operation mode operation sequence (timing): Effective sequence and cooperation relationship of each signal

(1) Synchronous Mode
• Sending and receiving are at a unified pace, with a unified clock signal.
• The synchronous clock determines the sending and receiving time completely without a response signal.
• Example: Bus read Operations
(2) asynchronous mode
• The sender and receiver determine the speed at which the bus is transmitted based on their working speed
• No unified clock signal, master-synchronous msyn and slave-synchronous ssyn

• Msyn rising edge: master device startup Input
• Ssyn rising edge: data has been prepared for the slave device;
• Msyn descent: the data has been removed from the master device;
• Ssyn descent edge: Route data bus from the device
• Features: Each device operates at the desired speed, with high time utilization.

• Event C: ssyn Jing → msyn flood
• Event R: msyn success → ssyn success
• Full lock: With C and R
• Semi-interlocked: either C or R

(3) quasi-synchronization mode
Add an Asynchronous Method to the full synchronization mode.
There are synchronous clock and response signal lines. Synchronous Sampling response signal




Bus Operation Mode


Information exchange between various components of the microcomputer system is completed through the bus operation cycle. A bus cycle is generally divided into the following four stages.
① Bus request and arbitration phase: when multiple modules initiate bus requests, the arbitration institution must conduct arbitration to determine which module to assign the right to use the bus.
② Addressing stage: the module that obtains the right to use the bus. The address and related commands of the memory or I/O port to be accessed are issued by the bus.
③ Data Transmission Phase: data transmission is performed between the main module (the module that obtains control of the Bus) and other modules.
④ End stage: the main Module removes the relevant information from the bus, and the main module gives control of the bus.