Bypass mode and PLL mode of DSP

"The input clock source to the DSP can be directly used to generate the clocks to other parts of the system (Bypass Mode) or it can be multiplied by a value from 2 to 15 and divided by a value from 1 to 32 to achieve a desired frequency (PLL mode ). the pllen bit of the PLL control/Status Register (pllcsr) is used to select between the PLL and bypass modes of the clock generator."

-Tms320vc5502 Datasheet

From the above description, we can see that the DSP clock source signal can be directly transmitted to other parts of the DSP to generate other parts of the clock, which is the bypass mode.

You can also multiply 2 ~ Any number between 15, divided by 1 ~ Any number between 32 to obtain the required frequency, which is the PLL mode.

The selection of Bypass mode and PLL mode is determined by the pllen module of pllcsr register (CSL under the PLL module.

Here, bypass mode is the default 5502 DSP mode.