Cache as Ram

1. Why need Cache?

The cache, also known as caching, is a small SRAM that is forced to add between the two to compensate for the increasing speed gap between the CPU and main memory. Modern processors typically have level three or level four caches, which are typically integrated on the CPU, which is often said to be L1 L2 L3 .... The cache works primarily for two reasons: a). The modern computer storage system of the mountain structure, in the mountain tip is the fastest storage equipment of course it is also the most expensive (such as cache), the bottom is the largest capacity of the slowest storage devices (such as hard disk). b). Computer access to data has a local principle, this time the quoted data may also be used frequently, and data near the location of the data is likely to be used. Based on the above two reasons, the cache mechanism is added to the CPU.

2. MTRR

Mention the cache can not fail to say MTRR,MTRR full name is memory Type Range registers, basically the cache related settings can be achieved by setting MTRR. MTRR, fixed range MTRR & Variable range MTRR Two types of registers are used to set the memory properties of the invariant ranges and the variable range of memory properties. About the Memory Properties section there are also UC WC WT WP WB These types, for a detailed introduction to MTRR please refer to Intel's trilogy:). We can tell the CPU how to access this space by setting the properties of the memory address range in the MTRR, but before we can set the CR0.CD bit to enable the cache.

3. Cache for Stack & Code

Intel's current processor basically supports configuring the CPU's cache to vr/w stack before memory is initialized (there are also limits to the number of addresses and ranges that can be configured), which is known as the cache as Ram. The code stack and data stack must be within the range of 4GB-64MB ~ 4GB, and the data stack must have at least an example of code region 4KB, and the size of region is limited by MLC and LLC. Of course, the code region must include at least the location of the Intel MRC presence. This mechanism, which is provided by the CPU, can achieve the following goals: 1. Speed up the speed of sbios, post time improvement that is very obvious who with who knows:). 2. Because there was a stack (SEC) early, it was possible to use high-level languages like C to write code, so that source code would be easier to write, and could be designed to be elegant and easy to understand. This is the end of the nonsense, stick to the principle of no figure without truth, the last basic flowchart as a conclusion:).

Cache as Ram