Cache command control in Loongson 2f and U-boot

00000 index Invalidate index_invalidate_i (I) 00001 index WriteBack Invalidate INDEX_WRITEBACK_INV _d (d) 00101 index Load tag index_load_tag_d (d) 01001 index Store tag index_s      Tore_tag_d (d) 10001 hit Invalidate hit_invalidate_d (d) 10101 hits WriteBack Invalidate           Hit_writeback_inv_d (D)//r10000-specific cacheops11001 Index Load Data index_load_data_d (d) 11101 index Store Data index_store_data_d (d) 00011 index WriteBack Invalidate index_write               back_inv_s (/D) (s) 00111 index Load tag index_load_tag_s (/D) (s) 01011 index Store tag index_store_tag_s (/D) (s) 10011 hit Invalidate hit_invalidate_s (/D) (s) 10111 hit WriteBack INV  Alidate hit_writeback_inv_s (/D) (s) 11011 index Load Data index_load_data_s (s) 11111 index             Store Data index_store_data_s (S) 

Index WriteBack Invalidate (S)   directive resets the corresponding block in level two cache to the invalid state. If the data for a level two cache block is dirty, write the data to the processor system interface part. Because the level two cache retains the inclusion relationship with the data cache and the instruction cache, the corresponding data in the data cache and the instruction cache is not valid until the level two cache invalidation is written back, and if the corresponding data in the data cache is dirty, it is first written to level two cache. Finally, the invalid writeback of level two cache block is completed. Pa[16:5] Defines the physical address, pa[1:0] defines an invalid group number. The
Invalid writeback operation is as follows:
1. The processor reads the stag and status bits from the tag array of level two cache. If the status bit state=00 (Invalid), no action is required. If the corresponding cache block is valid, STag is used to manipulate the instruction and the data cache.
2. Query instruction cache, if the itag=stag of the instruction cache and the state of the block in the instruction cache is istate=1 (Valid), the processor invalidates the corresponding block in the instruction cache, and the status is set to 0 (Invalid).
3. Query the data cache, if the data cache Dtag=stag and the data cache the state of the block dstate not equal to XX (Invalid), if the value of dirty bit is 1, the data is written to level two cache, invalid corresponding Cache block. If the value of the dirty bit is 0, the corresponding block of the data cache is directly invalid.
4. Set the status of the level two cache block to XX (Invalid). If the status of level two cache is one (Dirty), write the corresponding block back to the processor interface.

hit WriteBack Invalidate (S)   instruction level two cache the corresponding block matching the address PA is set to the invalid state. If the data for a level two cache block is dirty, write the data to the processor system interface part. Because the level two cache retains the inclusion relationship with the data cache and the instruction cache, the corresponding data in the data cache and the instruction cache is not valid until the level two cache invalidation is written back, and if the corresponding data in the data cache is dirty, it is first written to level two cache. Finally, the invalid writeback of level two cache block is completed. The
Invalid writeback operation is as follows:
1. The processor reads the stag and status bits from the tag array of level two cache with PA. A hit occurs if the value of the stag is the same as the value of the PA corresponding bit, and the status bit State is not equal to XX (Invalid). If no hit occurs, the cache instruction operation is complete.
2. Query instruction cache, if the itag=stag of the instruction cache and the state of the block in the instruction cache is istate=1 (Valid), the processor invalidates the corresponding block in the instruction cache, and the status is set to 0 (Invalid).
3. Query the data cache, if the data cache Dtag=stag and the data cache the state of the block dstate not equal to XX (Invalid), if the value of dirty bit is 1, the data is written to level two cache, invalid corresponding Cache block. If the value of the dirty bit is 0, the corresponding block of the data cache is directly invalid.
4. Set the status of the level two cache block to XX (Invalid). If the status of level two cache is one (Dirty), write the corresponding block back to the processor interface.

The hit Invalidate (S) command resets the corresponding block of address matching in level two cache to the invalid state. Because the level two cache retains the inclusion relationship with the data cache and the instruction cache, the data cache and the corresponding data in the instruction cache are not valid until the level two cache invalidation is written back, and the last two-level cache block is invalid.
The invalid operation procedure is as follows:
1. The processor reads the stag and status bits from the tag array of level two cache with Pa. A hit occurs if the value of the stag is the same as the value of the PA corresponding bit, and the status bit State is not equal to XX (Invalid). If no hit occurs, the cache instruction operation is complete.
2. Query instruction Cache, if the PA of the instruction cache matches the stag, and the state of the block in the instruction cache is istate=1 (Valid), the processor invalidates the corresponding block in the instruction cache, and the status is set to 0 (Invalid).
3. Query data cache, if the data cache is dtag=stag and the state of the block in the data cache is dstate not equal to XX (Invalid), the corresponding block of the data cache is invalid. 4. Set the status of the level two cache block to XX (Invalid).

Cache command control in Loongson 2f and U-boot