Call the Altera IP core emulation process-up

Call the Altera IP core emulation process-up

After studying this section, please read the simple simulation process based on Modelsim-se, as this section is designed based on the simple modelsim-se simulation process and the repetitive content involved in the process of designing the simulation process will no longer be detailed and will be If you delve into the section "simple simulation process based on Modelsim-se", the following will be very simple.

Writing RTL function codes

This section by calling the Altera ROM macro function module, the FPGA ROM module is mainly used for storing data, can be written (download) when power up, ROM module mainly contains three signals: clock, address, data, under the driver of the clock, to the ROM to write the address, The data side of the ROM outputs the data stored in the corresponding address. Using the simple simulation process based on Modelsim-se, the 8bit count generated by the 8bit counter is used as the address signal of the ROM module, and the ROM is addressed to the data stored in the output ROM.

On the basis of the 8bit counter module and ROM module, a new RTL file is created to map the two modules and output the data signals of the ROM output. The structure of the design is as follows:

Here's how to invoke the Altera ROM macro feature is not described in detail, here is a simple description of the ROM module parameter settings, data bit width of 8bit, storage depth of 256, as shown in.

Data output does not go through registers

The original storage file of the ROM is set, the Sin.mif file as the raw storage data, the SIN.MIF file stores 256 sine wave data, the data bit width and ROM data bit wide consistent.

Write the top-level RTL file, connect the two modules, and the code looks like this

Module Rom_top ( Class Reset_n, Rom_data ); Input CLK; Input reset_n; Output [7:0]rom_data; Wire[7:0]counter_out; Counter Counter_1 ( . CLK (CLK), . Reset_n (Reset_n), . Counter_out (Counter_out) ); Rom Rom_1 ( . Address (Counter_out), . Clock (CLK), . Q (Rom_data) ); Endmodule

Writing Testbench Code

The Testbench file uses a time unit and time accuracy of 1 NS/10 PS, the file's excitation input signal only needs to be assigned to the clock signal and the reset signal, and the output signal is the sine signal stored in the ROM. as shown below.

Testbench Code:

' Timescale 1 NS/10 PS Module ROM_TST (); Constants General purpose Registers Test Vector Input Registers Reg CLK; Reg Reset_n; Wires Wire [7:0]rom_data; Rom_top Rom_top_1 ( . CLK (CLK), . Reset_n (Reset_n), . Rom_data (Rom_data) ); Initial Begin Code that executes only once Insert code here--Begin Clk<=1 ' B0; Reset_n<=1 ' B0; --End $display ("Running testbench"); End Always Optional Sensitivity list @ (event1 or Event2 or .... eventn) Begin Code executes for every event on sensitivity list Insert code here--Begin #10 clk<=~clk; Reset_n<=1 ' B1; --End End Endmodule

Create a project

Run Modelsim by clicking Start-and-click Program->modelsim Se->modelsim or double-clicking the shortcut on the desktop, which appears as shown in the interface, if the previous project was built using Modelsim, This will automatically open the last project that was established;

Click on File->new->project and the interface shown will appear.

After you select project, the following interface appears in Project name, we enter the project name as ROM, click the Browse button in project location, select the path of the project save, note that Modelsim cannot create a directory for a project automatically. , it is best to choose a project folder that has been created as a directory, which library is compiled for our design in the default library Name, where the defaults are used, so that when the design file is compiled, work will appear in the Library of the Workspace window. Library. When we have finished typing here, click OK.

Click on the OK button will appear to select the simulation file interface, as shown, you can click on different icons to add different projects for the project, click Create New file to add new files for the project, click Add Existing file for the project to add the existing files, click Create Simulation to add a simulation to the project, click Create New folder to add the catalog to the project. Here we click Add Existing File;

The counter.v files, rom.v, ROM_TOP.V, ROM_TST.V files that were designed here are included in the project, and the IP Core library file must be included due to the call to Altera's IP core. The file for ALTERA_MF.V is also included in the project (this file can be found under the Eda/sim_lib folder in the Quartus installation directory). Click the browse button to include the file, as shown in, and then click the OK button.

It will then appear as shown in the Project work window of Modelsim, where two files have been included, where a question mark appears in the State column indicating that the file was included and not compiled.

Call the Altera IP core emulation process-up