Can three-channel +DDR3 be universal? Memory change in progress (next)

DDR3 to seize the class

1.8bit prefetching design, and DDR2 for 4bit prefetching.

Compared with the 4bit prefetching mechanism of DDR2 memory, the biggest improvement of DDR3 memory module is the design of 8bit prefetching mechanism, which is concurrent 8-bit data. At the same cell frequency, the data transmission rate of DDR3 is twice times that of DDR2. The frequency of the DRAM core is only 100MHz of the 1/8,ddr3-800 of the interface frequency, and when the DRAM core works at 200MHz, the interface frequency has reached 1600MHz. And when DDR3 memory technology matures, believe that the strength of the memory vendors will be introduced ddr3-2000 even more than 2400 of the frequency of memory.

Memory Specification Comparison Table

2. Use point-to-point topology to reduce the burden of address/command and control bus.

This is an important change to improve the performance of the system, but also a key difference between DDR3 and DDR2. In a DDR3 system, a memory controller deals with only one memory channel, and the memory channel can only have one slot, so the relationship between the memory controller and the DDR3 memory module is a point-to-point (point-to-point,p2p) relation (a single physical bank module), Or the relationship between point pair (point-to-two-point,p22p) (Dual physical bank module), which greatly reduces the load of address/command/control and data bus. In the memory module, similar to the DDR2 category, there are standard DIMMs (desktop pcs), So-dimm/micro-dimm (laptops), fb-dimm2 (server) points, The second generation of FB-DIMM will adopt a higher AMB2 (advanced memory buffer).

3. Using the following 100nm production process, The operating voltage from 1.8V to 1.5V, in the DDR3 system, for the memory system work is very important for the reference voltage signal Vref will be divided into two signals, namely the command and address signal Service VREFCA and for the data bus service VREFDQ, this will effectively improve the system data bus signal-to-noise level.

DDR3 is lower than DDR2 power consumption

4. Increase the asynchronous reset (reset) and ZQ calibration function. Resetting is an important new feature of DDR3, and a pin is specially prepared for this purpose. This pin will make the initialization of the DDR3 easier. When the reset command is in effect, the DDR3 memory stops all operations and switches to the smallest active state to conserve power. During reset, DDR3 memory will shut down most of the intrinsic functions, all data receivers and senders will be closed, all internal programs will be reset, DLL (delayed PLL) and clock circuits will stop working and ignore any movement on the bus. This will enable DDR3 to achieve the most energy-saving purposes.

The difference between DDR3 and DDR2

1, logical Bank number

The DDR2 SDRAM has 4Bank and 8Bank designs designed to cope with future demand for large-capacity chips. And DDR3 is likely to start with 2Gb capacity, so the starting logical Bank is 8 and is ready for the next 16 logical bank.

2, Packaging (Packages)

DDR3 due to a number of new features, so the pin will be increased, 8bit chip using 78 ball FBGA package, 16bit chip using 96 ball FBGA package, and DDR2 60/68/84 ball FBGA package three kinds of specifications. And the DDR3 must be a green package and cannot contain any harmful substances.

3. Addressing sequence (Timing)

Just as the number of delay periods increases as the DDR2 from the DDR transition, the CL cycle of DDR3 will also improve compared to DDR2. The CL range of DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional delay (AL) is also changed. At DDR2, the range of Al was 0 to 4, while DDR3 had three options for Al, 0, CL-1 and CL-2 respectively. In addition, DDR3 also adds a new timing parameter-write delay (CWD), which is based on the specific frequency of the work.

4, new features-Reset (reset)

Resetting is an important new feature of DDR3, and a pin is specially prepared for this purpose. The DRAM industry has long demanded that this feature be added, and is now finally being implemented on DDR3. This pin will make the initialization of the DDR3 easier. When the reset command is in effect, the DDR3 memory stops all operations and switches to the smallest active state to conserve power. During reset, DDR3 memory shuts down most of the intrinsic functions, so both the data receiver and the transmitter will be closed. All internal programs will be reset, the DLL (delayed PLL) and the clock circuit will stop working and ignore any movement on the data bus. This will enable DDR3 to achieve the most energy-saving purposes.

5, automatically refresh according to the temperature (Srt,self-refresh temperature)

To ensure that the saved data is not lost, DRAM must be refreshed periodically, DDR3 is no exception. However, in order to save the greatest power, DDR3 adopts a new type of automatic self refresh design (asr,automatic Self-refresh). When ASR is started, a temperature sensor that is placed in a DRAM chip will be used to control the frequency of the refresh, as the refresh rate is high, the power dissipation is large, and the temperature increases. While the temperature sensor to ensure that the data is not lost, as far as possible to reduce the refresh frequency, reduce operating temperature. However, DDR3 ASR is an optional design and does not necessarily mean that the DDR3 memory on the market supports this function, so there is an additional function of the Self Refresh temperature range (Srt,self-refresh temperature). With a pattern register, you can select two temperature ranges, one is a normal temperature range (for example, 0 ℃ to 85 ℃), and the other is an extended temperature range, such as up to 95 ℃. For both of these temperature ranges set in DRAM, DRAM will be refreshed with constant frequency and current.