Chapter 2. External Bus Chapter 2. interrupt handling

Chapter 4. External Bus
The external bus provides external device addressing and can read and write code and data on 51mx devices. The external bus uses the same classic 80C51 multi-channel external bus and allows an additional 23-bit output address.
4.1 multi-channel External Bus
The 51mx External Bus supports 8-bit data transmission and 23-bit address port lines. You need to configure the valid number of corresponding port lines by setting the EAM bit of the mxcon register. The default value is the 16-bit address bus, which can be successively compatible with the existing 80C51 socket.
The software changes the bus configuration information by setting the EAM bit = 1 in the mxcon register. It is generally not recommended to change the port Line Address Configuration During program execution. (For example, changing EAM = 1 to 0 in program execution will change the bus interface, and the chip will not be able to access the external space );
When P2 port multiplexing address bit 23 (EAM = 1), high address (address16 ~ Address23) and low address (address0 ~ Address7) will be locked to a fixed external space through the lock ale, when the intermediate address (address8 ~ Address15) after the arrival of ale will not be locked, three byte addresses are merged into the total address. If the EAM bit of the mxcon register is not 1, it works the same way as 80C51.
There are two special P2 port multiplexing methods for addressing external spaces (EAM = 1, mxcon). movx @ RI and movx @ dptr commands do not provide 23-bit addresses for all resources, when using the program storage address movc, any missing address bit is filled by the PC, and all missing address bits of movx are forcibly filled with 0 to 23 bits, therefore, these commands are used to obtain the low storage space of xdata. Therefore, the movx @ Ri address ranges from 8-bit high to zero, the 8-bit padding is zero + the 8-bit padding is Ri content to form a 23-bit address value. Movx @ dptr: The address is composed of the content of the dptr with a full Zero height of 8 bits + 16 bits. The movx State described in this section is valid under the EAM = 1 setting. Only in this way can the P2 port be reused with a 23-bit address. Otherwise, the address is still in the 16-bit addressing mode of 80C51.
If you have special requirements for using the 23-bit address interface and off-chip code, you can use software settings. If this method is used: run some code and then modify the configuration. If EAM = 1, the command must be fixed or the address is <00fbh. Because when the configuration changes to a 23-bit address, it is necessary to prevent the external bus from providing a 16-bit address. If the jump address of the PC counter is 0100 when EAM = 0 (the external hardware still expects a 23-bit address), the provided address will change to and an error will occur. Therefore, when the flag is set to 0 in the intermediate address, the 16-bit or 23-bit addresses are the same.
Now, we plan to use the 23-bit wide address of 51mx, which is the same as the 80C51 interface, to develop applications mapped to the same space memory. We must abide by some programming rules, set the EAM flag to 1 for the 51mx external memory access interface,
If you use the P2 port and RW, RD control line for memory ing, you do not need to change it compared to 51. You only need to use the 16-bit lower address on the current 23-bit address bus.
The memory ing device uses the descent edge to trigger the ale controller to lock the 16-bit address. The movx @ RI/dptr command cannot use the emov @ PRI; the lower 8-bit address of P0 and the higher 8-bit address of P2 port are locked when the ale drops. The correct memory ing device address is expected to be valid. When the P2 address8 ~ When the address15 address is valid, WR/RD is executed along the descent. the movx @ RI/dptr command will cause a high value to change to 0, which will cause device access problems. To avoid this problem, use pr0: R3 = R2, PR1: r7 = R5, the P2 output is both the ale descent edge and the RD/WR descent edge. The memory ing device will find the correct address.

Ale: the lock address function. This semaphore directly locks the address port. It may be data or Code address.
Psen: the output signal end of the program storage. It can read the instruction code in the EPROM/ROM in the range of-7f: FFFF. If it is a general-purpose memory ing, the corresponding address range is 80: 0000-ff: FFFF.
RD: External Data Reading signal, connecting to RD peripherals
WR: writes external data signals and connects WR peripherals.
The external data bus address ranges from ~ 7f: FFFF matches the General ing memory address. If the in-chip address is activated, the external address cannot be used, and all data/idata are in the disk.
Chapter 4. interrupt handling:
P87c551 provides four priority and interrupt processing types, which can effectively source various interrupted resources. P87c551 provides 11 interrupt sources.
Each opposite interrupt source is enabled or disabled by setting a bit of the Int or int1 register. int0 contains a Global interrupt control bit EA: it can control whether all interrupts are valid.
Each interrupt source can be set to one of the four priority levels through ip0, ip0h, IP1, and ip1h. A high-priority interrupt can seize the current low-priority interrupt, while a high-priority interrupt cannot. Interruptions with other priorities cannot take the highest priority. If a request is interrupted with different priorities, the service is interrupted with a higher priority.
00 is the lowest priority interrupt attribute, and 11 is the highest priority attribute. For example, the time0 interrupt priority attribute is controlled by in0 and in0h bits. If in0h = 1, if in0 = 0, the priority attribute of time0 is 10, which is 2.
If two requests with the same priority are interrupted at the same time, the service to be executed will be selected in turn. This will be the priority arbitration. Note that priority arbitration will only be requested when the same priority is interrupted at the same time.