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2.3 Special Function registers
Special Function registers provide a way for the processor to access internal control registers, peripherals, and I/O Ports. A special function Register address is always included in a single instruction.
The space of the standard special function registers is 128 bytes in size. To provide control over peripheral devices or access to CPU features and functions, special function registers are implemented on every 51mx device as needed. Undefined special function registers are reserved and should not be accessed by user programs.
The 16 addresses in the register space with special functions are both byte and bit addressable. The special functional registers with bit addressing are those addresses ending with 0 h or 8 h (that is, 80 h, 88 h ,..., F8h ). Bit addressing allows you to directly control and test the bit of those special function registers. All 51mx devices also have additional 128-byte extended special feature registers (discussed in 51mx architecture reference ). Figures 8 and 9 show the ing between special function registers and extended special function registers for the p89c669 section.
2.4 external data storage (xdata)
The xdata space of 51mx is the same as the 64 kB external data storage space on the classic 80C51.
In-chip xdata storage can be disabled by using the extram bit of the auxr register under program control. By default, xdata accessed from the above implementation will be directed to the external bus. If the xdata storage in the slice is disabled, all the xdata access will be directed to the external bus. P89c669 has 768 bytes of xdata in the disk.
2.5 high-end data storage (hdata)
The 51mx architecture uses 23-bit addressing and supports up to 8 mb data storage space. The rest of the edata space that has exceeded 64 kB in 8 Mb space is called hdata. The xdata space contains 64 KB of hdata.
The Data Pointer 51mx adds a 23-bit Extended Data Pointer (eptr) to allow the existing 80C51 program to use data storage that exceeds 64 KB ). If we want to access a separate Data byte located in the hdata ram that is located beyond the first 64 kB range, the EAM bit (eax = 1) in the mxcon special function register must be set ).
All 80C51 commands using dptr have a 51mx variant using eptr. The 23-bit eptr consists of (in order) Eph, PEM, and EPL special function registers. Figure 10 and 11 show examples of indirect access to data storage using dptr and eptr, respectively. Because eptr is 23 bits, the 8th bits of Eph are not used. If read, it returns 1, as if it were not implemented in a special function register. Eptr can be operated as a 23-bit register or three independent 8-bit registers. Use eptr to allow access to the entire hdata space, including xdata. At any time, a specified Data Pointer is active and used by commands related to dptr. The Active Data Pointer (dptr) is composed of a high byte (DPH special function register) and a low byte (DPL special function register, and its purpose is to save a 16-bit address. However, it can be operated as a 16-bit register or as two independent 8-bit registers. The active dptr can be selected by changing the Data Pointer selection (DPS) bit. The DPS bit occupies the base position of auxr1. DPS bit is only applied to two dptr, not eptr.
In indirect addressing mode, the active dptr or eptr provide a data storage address for accessing xdata and hdata respectively. When dptr is used for addressing, only xdata space is available. When eptr is used for addressing, the entire hdata space (including xdata space) can be accessed. If the eptr value exceeds the limit of 7e: FFFF (hdata), data access using eptr will cause undefined results. The hdata address is restricted to ensure the consistency of eptr addressing and general pointer addressing (strong in later sections of this article.
80C51 and 51mx are both "Harold" architectures, meaning that the code and data space are separated. If the size of one executable code exceeds 64 KB, the EAM bit of the mxcon special function register must be set (EAM = 1 ). Similarly, if a code constant exceeds the 64 kB boundary and is to be read by the application, the EAM bit must also be set to (EAM = 1 ).
The 51mx architecture extends the 80C51 program counter to 23 bits, providing a continuous, non-segmented linear code space, which may be 8 Mb in size. The in-chip space starts from the Code address 0 and extends to the limit of In-chip code storage. Beyond this limit, the code will be obtained from outside the credits. The 51mx architecture provides an external bus. It supports:
· Hybrid mode (some off-chip code and/or data storage)
· Single-chip operation (no external bus connection)
· No rom operation (No in-chip code storage is used)
In some cases, code storage can be addressed as data. The extended instruction addressing mode allows you to access the entire 8 Mb code space by using indexed indirect addressing. The currently active dptr, eptr, universal pointer, or program counter can be used as the base address. Figures 12 to 24 show examples of different code storage addressing modes.
After the reset, p89c669 starts code execution from address 00: Running H like the classic 80C51. Similarly, the interrupt vector is placed above the reset address, starting from address 00: 0003h. Note that the First Command (at address 0) should not be an ejm command. Ejmp is a 5-byte command that overlaps the external interrupt vector 0 at the address 00: 0003h.
2.7 universal pointer
Specifically, to enhance the code density and performance of C language in a large program, a new addressing mode called Universal pointer mode has also been added to 51mx. This addressing mode allows you to use an instruction to access code and data spaces in and out of the chip without further understanding of which data is in different spaces. This includes data, idata, edata, xdata, hdata, and code space. The SFr space is the only space that cannot be accessed using a universal pointer.
The general pointer addressing mode uses a new set of pointer registers for two reasons. The first is to allow addressing of 8 Mb code space and 8 mb data space, which requires 24-bit pointers. The second reason is that the multi-byte data in the Operation register is more effective than that in SFr. The C compiler actually performs pointer operations in the Register, and then moves the result to the Data Pointer for use.
Two common pointers are supported: pr0 and PR1. The pr0 pointer consists of the registers R1, R2, and R3 In the current Register "stack", and the PR1 consists of the registers R5, R6, and R7 in the current Register "stack. See Figure 15.
To access all different buckets in a single and unified way, these buckets must be mapped to a new view with a total size of 16 Mb. This new view is called general storage ing. The xdata space is placed at the bottom of the new address ing. The hdata space is followed by the xdata space. The standard internal data storage space (data and idata) is above hdata, followed by the edata space. Finally, the Code bucket occupies the top part of the ing. Therefore, the highest valid bit of a universal pointer determines whether to access the code or store data. By placing the xdata space at the bottom of the universal storage ing, the address of the universal pointer from 00: 000h to 00: ffffh can be consistent with the external data storage space of the classic 80C51. This provides full upward compatibility when no more than 64 KB of external data space is required. Figure 16 shows the general storage ing. Figure 17 shows the standard storage space and how the General pointer is related to the value of the general pointer. Only a new emov instruction of 51mx is used. The emov command allows you to use a common pointer to move data into or out of the accumulators. You can specify the offset of 0, 1, 2, or 3, whether it is moving in or out. This offset will add the pointer used previously. The offset allows the C compiler to access a variable with a maximum of four bytes (such as a long integer) without changing the pointer value ). Figure 18 shows an example of common pointer usage. Note that it is impossible to save the value in the code area of the general storage ing. Another newly added command allows the value 1 to 4 to increment any common pointer. This allows the pointer to point to the next data element over the last accessed data element.
Generic pointers are designed to facilitate addressing in the extended addressing mode (when the bit EAM in mxcon is set. Then, the generic pointer can still be used when EAM = 0. In this case, generic pointer addressing can only access the 64 kB code space and the 64 kB xdata space at the bottom. The value of a universal pointer pointing to these areas cannot be changed. When EAM is set to 0, the FFH is returned when a universal pointer accesses inaccessible areas outside of these areas.
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