Chapter 6 beautiful start-stream and stream

According to Windows-based languages (C, C ++, C #), etc.Programming LanguageThe first course should be "Hello World !" . However, this routine will be introduced in the subsequent articles of association due to the hardware drive difficulty. The first routine for hardware engineers to learn about the Development Board: A fl lamp, a great start.

This chapter willCodeAt the same time, I will explain the use of Quartus II software. In the subsequent sections, I will only talk about the software ideas and solutions, and I will not make too many redundant descriptions.

1. Step by step to build the first project

(1) Create the first project, file-new Quartus II project, as shown in, OK.

(2) Next, as shown in, select the project directory (no space, Chinese path), and enter the project name and top-level file name.

(3) If there is a ready-made code, you can directly add the code to the project; otherwise, directly click Next to go to the next step, as shown in:

(4) select the target device based on your hardware.

(5) Next, finish.

Ii. Engineering Code Design 1. water_led_design project file structure:

As shown in, the project is divided into three modules:

(1) Top-level module: examples of each module, the highest level of project files.

(2) frequency division module: obtains a fixed frequency (10Hz) through the frequency division ).

(3) LED Display Module: operate LED lights at a fixed frequency.

2. Code Design

(1) warter_led.v Module Design

A) New-file: Create a new OpenGL file and save it in the SRC folder created in the project directory (only for the sake of clear structure of the project file and better management ). As shown in:

B) enter the code to define the input and output interfaces, as shown below:

Module water_led

(

Input CLK, // global clock 50 MHz

Input rst_n, // global clock reset

Output [5:0] led_data // user led Interface

);

Endmodule

(2) clk_design.v Module Design

Because the input clock of the system is 50 MHz, if the LED is changed at a speed of 50 MHz, the human eyes cannot tell it. Therefore, the 50 MHz frequency is used to adapt to human eyes. This module divides 50 MHz to 10Hz, and the maximum resolution of human eyes is 25Hz, so 10Hz can be felt (can be modified randomly ). Formula for Calculating the frequency of led_en: clk_led_en = 50_000000/(49_000000 + 1) = 10Hz. The Code is as follows:

Module clk_design

(

Input CLK,

Input rst_n,

Output led_en

);

Reg [] CNT; // 49_99999, 100 ms

Parameter led_cnt = 49_999999;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

CNT <= 23 'd0;

Else if (CNT <led_cnt)

CNT <= CNT + 1' B1;

Else

CNT <= 23 'd0;

End

Assign led_en = (CNT = 23 'd49 _ 99999 )? 1 'b1: 1' B0;

Endmodule

The module generates a 10Hz enable clock instead of a 10Hz frequency. The purpose is to prevent the clock from flying over the sky, so that the internal layout of FPGA wiring is disordered and global functions are affected. Although such a simple project does not need to be considered, "being used to rigor has become a kind of style". Therefore, the Enable clock is used to operate the specific time series. The differences and advantages of the clock enabling and clock switching mechanisms will be described in the subsequent sections.

(3) Design of led_display.v Module

According to the input led_en enabling signal, to operate the LED light effect, here use the simplestAlgorithm-- Incremental carry. The Code is as follows:

Module led_display

(

Input CLK,

Input rst_n,

Input led_en,

Output Reg [5:0] led_data

);

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Led_data <= 6'b0;

Else if (led_en)

Led_data <= led_data + 1 'b1;

Else

Led_data <= led_data;

End

Endmodule

(4) modify the water_led_design top-level file and add related sample modules. The final result is as follows:

Module water_led_design

(

Input CLK, // global clock 50 MHz

Input rst_n, // global clock reset

Output [5:0] led_data // user led Interface

);

//-------------------------

// Generater clock 10Hz

Wire led_en;

Clk_design clk_design_inst

(

. CLK (CLK ),

. Rst_n (rst_n ),

. Led_en (led_en)

);

//-------------------------

// Set the display of LED

Led_display led_display_inst

(

. CLK (CLK ),

. Rst_n (rst_n ),

. Led_en (led_en ),

. Led_data (led_data)

);

Endmodule

3. code compilation

(1) Use processing-start compilation, or the toolbar icon is as follows:

(2) The compilation result is as follows:

(3) warning analysis and solution:

A) warming (4) is shown in. The specific explanations are as follows:

I. No capacitor Configuration

II. the unused pin is not set to three States. Set assignment-device and pin opitions-unused pins, as shown in:

Iii. No capacitor Configuration

Iv. Ignore

B) Critical warming (5) is shown in. The specific explanations are as follows:

I. No Io is assigned to the pin.

Ii. There is no SDC Timing Constraint File

Iii. No SDC constraint File

Iv. Timing does not meet requirements

V. The timing sequence does not meet the requirements

The reason for these warnings is that the Software Versions later than Quartus II 10.1 no longer comes with timequest Timing Analyzer, and only classic Timing Analyzer. Although SDC timing constraints are not added, they are not always wrong in general, however, this warning is inevitable in software design. The timingquest SDC will be described in subsequent sections.

For Quartus II warning information analysis and zero warning processing, right-click the warning to view help, and Altera will tell you the corresponding solution. In addition, Bingo has uploaded chinaaet "Quartus II warning analysis warning ", is: http://www.chinaaet.com/lib/detail.aspx? Id = 86271

You can refer to the PDF document if you cannot get started with the discount. Remember, never ignore the warning easily.

Iii. Modelsim-Altera simulation 1. Why should we simulate it?

First, we will discuss two issues:

(1) simulation? Is it true?

Simulation is just to simulate the real phenomenon, test the code behavior and the correctness of the timing; of course, simulation is always imitation, it cannot be absolutely accurate, but can only simulate the real time series to a certain extent, make our design more reliable. Simulation is only a software testing platform for circuit designers, rather than the testing results of actual hardware facilities.

(2) must we simulate it?

Not necessarily! If you have enough time series accuracy to complete the timing logic workflow of the entire circuit, simulation is not necessary, when the time sequence is accurate, why the simulation in vain? In common sense, it is the existing Quartus II software. If we have another simulation software, testbench is just a test.Program, Link the bridge between the two.

In retrospect, it seems difficult for an old engineer to design a schematic using blocks and non-door and 74 series chips N years ago to perform simulation? Those elders are constantly correcting and improving physical tests to obtain reliable circuits.

Therefore, simulation is not required. Bingo is often not simulated! This is not to say that it is lazy because of the circuit timing logic in the mind, which can ensure the accuracy of the circuit, or can correct the problem on its own without losing the direction. The so-called code on the computer, the circuit in the brain, every behavior-level language, add a circuit.

Of course, not everyone can. For beginners, simulation is a very important process. The reason is that, in the minds of beginners, there is no time sequence workflow implemented by fixed logic. In other words, there is not enough experience.

Of course, timing simulation is required when the timing sequence is complex and huge, because in this case, the simulation of the brain may not be able to match the computing speed of the computer.

As mentioned in the section on installing Quartus II software earlier than Quartus II 9.1, the software comes with a simulator, and later than 9.1 requires support from third-party software. Third, there are a lot of simulation software, and the most used is, of course, Modelsim-Altera. In this section, quartuus II 11.0 works with Modelsim-Altera to simulate and test the code sequence of this routine. We hope to have a deeper understanding of the timing logic through the analysis of sections.

2. knowledge required for Simulation

Altera_modelsim simulation data: http://www.chinaaet.com/lib/detail.aspx? Id = 86257

Iv. Configure fpga1.

The configuration pin is simply to map the internal logic signal of FPGA to I/O through software settings. The specific methods are as follows:

(1) manually input the IO pin in assignments-pin Planner

(2) manually input Quartus ii tcl console in the format of "set_location_assignment pin_28-to CLK"

(3) Tcl scripts, ing by calling the Tcl File

(4) In assignments-import assignments, ing is performed by calling a file in the (2) format.

The following two methods specific steps can be seen in the user's "hours do not know the month" Web Tutorial: http://www.cnblogs.com/yuphone/archive/2010/01/18/1650612.html

View the pin us II pin planner, as shown in:

After the pins are configured for integration, the above two warnings are missing.

NOTE 1: For the pin configuration method in Quartus II, if you manually enter the configuration using the original first GUI, You need to compile the software for generating Io on the pin planner after the first compilation, then manually configure it in the GUI. If you use the other three methods, you can use the command to enter the configuration information before the first compilation. After us II is compiled, the ing information is automatically identified, achieve the same effect.

NOTE 2: For the system and FPGA design, because of the large project size and many pins, compilation and synthesis usually takes a lot of time. Therefore, the first method is not used, besides, the ing information is imported before the first compilation.

2. Target Board download Mode

All in all, the Quartus II software is just a GUI user terminal used to design code and integrate FPGA logic circuits. The ultimate goal is to download it to the target board through USB bluster, parallel port or other means. There are the following types:

(1) Configure FPGA--JTAG Mode

The so-called configuration of FPGA is to configure the sof file circuit to the FPGA's SRAM (FPGA is based on the SRAM format), and conduct on-site configuration and verification without power loss. This method is downloaded through the JTAG interface.

(2) burned out the source of the New Source-active serial programming.

The so-called "Burn-in" function is to generate code information and install it into the storage chip. By configuring signals or powering on again, you can configure fpga sram, therefore, power loss (similar to CPLD) is not lost in the PV ). There are two methods to burn the PV:

A) download the POF file through the ASP interface

B) download the JIC/JAM file through the JTAG interface. The JIC/JAM file is obtained after the sof file is converted by Quartus II software.

(3) Concurrent passive serial download

(4) download in socket programming

The above two models are not described too much here because they are not widely used.

In summary, the ASP interface can be removed and replaced with JTAG when the cost is sensitive or the board space is harsh. The reason for the design of the two interfaces is that it gives users greater selectivity. In special cases, only the ASP interface can exist, and only one download is performed, instead of the JTAG interface for testing.

3. Download JTAG

(1) Open programming in the toolbar or in the menu bar tool.

(2) If hardware is not found, find the USB bluster in hardware setting.

(3) Select JTAG Mode

(4) If the sof file is not automatically loaded, click Add file to import the sof file of the project.

(5) Click Start and wait for the download to complete, as shown in:

4. Download Apsara stack management framework

(1) In ASP mode

A) switch mode to active serial programming mode.

B) change file is a POF file.

C) Click Start and wait until the download is complete. Because flash is slower than SRAM, download is slower than flash.

At this point, we can see that the flow lights on the target board are gradually turned on.

(2) In JTAG Mode

A) use the sof file automatically generated by Quartus II to convert it to a JIC file through software. The steps are as follows:

I. Open File-convert programming file.

Ii. Select the JIC file in programming file type.

III. In configuration device, select the model of the target board.

Iv. File name can be modified by default or arbitrarily

V. select Flash loader in file/data area, click Add device on the right side, find the FPGA of your own model, and confirm.

Vi. Select sof data in file/data area, and click Add file on the right side to load the sof file under the project directory.

VII. Select the loaded sof file in file/data area, click Properties on the right side, select compression (compression), and confirm. (This step can be omitted to increase the download speed if the size of the PV is allowed)

VIII. Click Generate to generate the JIC file, as shown in, and close the file.

B) Open programming and select JTAG mode.

C) Select the JIC file generated earlier, and select Program/configure next to the JIC file.

D) Click Start and wait for the download to complete, as shown in:

At this point, we can see that the flow lights on the target board are gradually turned on.

5. Programming/configuration Failure Causes

(1) the USB download loader is not properly connected or the USB cable is too long (not plugged in, or the interface is inserted incorrectly)

(2) the device is not powered on.

(3) Incorrect FPGA device model selection

(4) Incorrect Model Selection

(5) Poor layout and wiring, resulting in incorrect download Sequence

(6) FPGA chip damaged

(7) The PV chip is damaged.

(8) damaged USB bluster