Chapter 7 of pci_express specifications-software initialization and Configuration

7. software initialization and Configuration

PCI Express configuration model supports two access mechanisms:

-PCI-compatible configuration mechanism: the binary 100% is compatible with those defined in PCI 2.3 and with earlier operating systems or similar bus enumeration and configuration software.

-Enhanced configuration mechanism of PCI Express: provides more effective configuration space and more effective access mechanism.

7.1 configuration Topology

-PCI Express Link: A link represents a dual-simplex communications channel between two components.

-Root complex:RCMain functions andPCIIn the busHostThe main bridge is similar,HostMany functions are added on the basis of the main bridge.

7.2 PCI Express configuration mechanisms

PCI Express configuration space diagram:

-1.pci express extends the configuration space specified in PCI spec 2.3 From 4096 bytes to bytes.

-2.pci express configuration space is divided into two parts:

-- 1.pci 2.3 compatible, which contains the first 256 bytes of the configuration space of each logical device.
-- 2.pci express extensions, including the remaining regions.

-3.pci 2.3 compatibility can be accessed using any access mechanism defined in PCI 2.3, or using the configuration access method defined in PCI Express (described later ).

-In section 4.pci Express, only PCI Express configuration access mechanisms can be used.

The access method for the PCI 2.3 compatibility section is as follows:

1. Each PCI device has its unique PFA (pCI function address). PFA is composed of bus number, device number & function number. For example:. USB device PFA is (0, 6, 0) <-USB is a PCI Device and Its bus/dev/function is 0/6/0.

-- With PFA, you can access its PCI configuration registers.

Ex. Write usb pci register 43 H bit1 = 1

MoV eax, 80003040 H
MoV dx, 0cf8h
Out dx, eax

MoV dx, 0 cffh
In Al, DX
Or Al, 00000010b
Out dx, Al

Access to. PCI Express extended space:
Ex. moV ax, [50400000 H] <-Read Device (, 0)'s register 0; 2 bytesnote: PCIe extended base address to reserve and report to OS. size is 256mbyte. this is what BIOS needs to do. (Of course, the BIOS also needs to import the base address into the chipset register to let the chipset know that when such a cycle exists, it is for the PCIe device! )-Some traditional Chinese characters are from the network.

Here 50000000 H: PCIe extended base address. You can learn from chipset register
Bit [27:20]: Bus Information
[19: 15]: device information
[14: 12]: function Information
[11: 8]: Extended register
[7: 2]: DW number
[1:0]: byte enable

Therefore, as long as you know the PCIe extended base address, you can access PCIe config registers as before, that is, you can access 0ffh.

Note: In fact, PCIe devices can be identified by capabilities pointer register in the PCI 2.3 compatibility section, because there will be a PCIe capability in many capabilities; its id value = 10 h.

ID	Description
00 h	Reserved.
01 H	PCI Power Management Interface. Refer to "the PM capability register set" On page 585.
02 h	AGP. Refer to "AGP Capability" on page 845. also refer to the mindshare book entitledAGP system architecture, Second Edition(Published by Addison-Wesley ).
03 h	VPD. Refer to "vital product data (VPD) Capability" on page 848.
04 H	Slot Identification. This capability identifies a bridge that provides external expansion capabilities (I. e., an expansion chassis containing add-in card slots). Full documentation of this feature can be found in the Revision 1.1PCI-to-PCI bridge Architecture Specification. For a detailed, express-oriented description, refer to "Introduction to chassis/slot numbering registers" On page 859 and "chassis and slot number assignment" On page 861.
05 h	Message signaled interrupts. Refer to "the MSI capability register set" On page 332.
06 h	CompactPCI Hot Swap. Refer to the chapter entitledCompact PCI andPMCIn the mindshare book entitledPCI system architecture, Fourth Edition(Published by Addison-Wesley ).
07 h	PCI-X Device. For a detailed description, refer to the mindshare book entitledPCI-X System Architecture(Published by Addison-Wesley ).
08 h	Reserved for AMD.
09 h	Vendor Specific capability register set. The layout of the register set is Vendor Specific, doesn't that the byte immediately following the "Next" pointer indicates the number of bytes in the capability structure (including the ID and next pointer bytes ). an example Vendor Specific usage is a function that is configured in the final manufacturing steps as either a 32-bit or 64-bit PCI agent and the vendor specific capability structure tells the device driver which features the device supports.
0ah	Debug port.
0bh	CompactPCI central resource control. A full definition of this capability can be found in the PICMG 2.13 specification (http://www.picmg.com ).
0ch	PCI Hot-plug. This ID indicates that the associated device conforms to the standard hot-plug controller model.
0dh-0fh	Reserved.
10 h	PCI Express capability register set (Aka PCI Express capability structure). For a detailed explanation, refer to "PCI Express capability register set" On page 896.
11h-ffh	Reserve

3.8.2.12 hecbase-PCI Express extended configuration base address register
This register defines the base address of the enhanced PCI Express Configuration
Memory.

device: 16
function: 0
offset: 64 h
Version: Intel 5000 P chipset, Intel 5000 V chipset, intel 5000z chipset
bit ATTR default description
31: 24 RV 0 h reserved

23:12 RW 001 H hecbase: PCI Express extended configuration base this register contains the address that corresponds to bits 39 to 28 of the base address for PCI Express extended configuration space. configuration Software will read this register to determine where the 256 MB range of addresses resides for this particle host Bridg E. this register defaults to the same address as the default value for tolm.
11: 0 RV 0 h Reserved

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