Chapter 8 unity of opposites-asynchronous Clock Synchronization

I. What is unity of opposites?

What is the CEO? The Chief Executive Officer is the most senior manager responsible for daily operation and management in an enterprise, also known as the chief executive officer, or the top executive or large class.

In FPGA systems, there is no need for a senior executive to manage all processes? For the sake of system orderliness, there will be no disorder or breakdown, and the answer must be yes.

Everyone knows that the work of FPGA's internal timing logic is completed by the combination of clock. So what if there is an asynchronous clock in the system? Each system must have a clock of the highest level, with the strongest execution ability. At the same time, it is responsible for managing the asynchronous clock. Other asynchronous clocks must be told to the executive officers to execute tasks, then the executive will assign the task. Therefore, all actions must be performed only with the permission of the Chief Executive Officer. Otherwise, there is no way to proceed. The Chief Executive Officer has the highest right of support. Shows the relationship between them:

Therefore, the asynchronous clock in the project is in opposition to the highest clock, but the CEO's position determines that only he has the right to say it, otherwise it will be "rebellion ", therefore, the asynchronous clock should be managed in a unified manner, which is called "Unity of Opposites ".

Ii. asynchronous clock synchronization 1. asynchronous clock types

There are many types of asynchronous clocks. The following are common cases in several projects:

(1) Asynchronous Reset signal of the system

(2) clock input by other Processors

(3) Clock generated by the internal combination logic

Of course, not all asynchronous clocks need to be synchronized. High-Speed ADC is required. The DAC chip usually has a clock input. At this time, the chip can be synchronized with the logic circuit and can be used to provide a crystal oscillator, to achieve better results. At the same time, the clock other than the highest clock must be synchronized. The different clocks generated by the PLL are synchronized and can not be processed.

Of course, when the reliability requirement is not high, Asynchronous Reset of these signals can also not be processed, but, to form a good habit, will never be wrong.

2. asynchronous clock Solution

The Clock Synchronization Methods are similar. Bingo was inspired by the privileged "getting started with FPGA" and briefly described the synchronization of several Asynchronous Reset signals.

(1) Asynchronous Reset signal synchronization

This part is actually very simple. I applied some of the above-mentioned thinking about edge detection, and used the highest clock to take a few slow beats to synchronize it with the highest clock. Block is no longer used here as a cumbersome description.CodeAs follows:

/*************************************** **************

* Module name: synchronism_design.v

* Engineer: crazy bingo

* Target device: ep2c8q208c8

* Tool versions: Quartus II 11.0

* Create Date: 2011-6-25

* Revision: V1.0

* Description:

**************************************** *************/

Module synchronism_design

(

Input CLK,

Input rst_n,

Output sys_rst_n

);

//------------------------------------------

// Rst_n synchronism, is controlled by the input CLK

Reg rst_nr1, rst_nr2;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Begin

Rst_nr1 <= 1 'b0;

Rst_nr2 <= 1 'b0;

End

Else

Begin

Rst_nr1 <= 1 'b1;

Rst_nr2 <= rst_nr1;

End

End

Assign sys_rst_n = rst_nr2; // active low

Endmodule

The RTL diagram of Quartus II is as follows:

(2) Asynchronous Reset signal synchronization during PLL collaboration

Compared with the expansion of the Asynchronous Reset signal synchronization method, the signal processing in the case of a PLL ring is analyzed. As shown in the following code, the Asynchronous Reset signal is synchronized with the crystal oscillator input clock. Finally, the final system reset signal is obtained by synchronizing the locked signal with the PLL output signal with the previous reset signal and operation.

The following is the specific example of the Code:

/*************************************** **************

* Module name: synchronism_pll_design.v

* Engineer: crazy bingo

* Target device: ep2c8q208c8

* Tool versions: Quartus II 11.0

* Create Date: 2011-6-25

* Revision: V1.0

* Description:

**************************************** *************/

Module synchronism_pll_design

(

Input CLK, // 50 MHz

Input rst_n, // global Reset

Output sys_rst_n, // system reset

Output clk_c0 // 50 MHz

);

//----------------------------------------------

// Rst_n synchronism, is controlled by the input CLK

Wire pll_rst;

Reg rst_nr1, rst_nr2;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Begin

Rst_nr1 <= 1 'b0;

Rst_nr2 <= 1 'b0;

End

Else

Begin

Rst_nr1 <= 1 'b1;

Rst_nr2 <= rst_nr1;

End

End

Assign pll_rst = ~ Rst_nr2; // active high

//----------------------------------------------

// Sys_rst_n synchronism, is control by the highest output CLK

Wire locked;

Wire sysrst_nr0 = rst_nr2 & locked;

Reg sysrst_nr1, sysrst_nr2;

Always @ (posedge clk_c0 or negedge sysrst_nr0)

Begin

If (! Sysrst_nr0)

Begin

Sysrst_nr1 <= 1 'b0;

Sysrst_nr2 <= 1 'b0;

End

Else

Begin

Sysrst_nr1 <= 1 'b1;

Sysrst_nr2 <= sysrst_nr1;

End

End

Assign sys_rst_n = sysrst_nr2; // active low

//----------------------------------------------

// Component instantiation

PLL

(

. Areset (pll_rst ),

. Inclk0 (CLK ),

. C0 (clk_c0 ),

. Locked (locked)

);

Endmodule

The RTL us ii rtl diagram is as follows:

(3) asynchronous signal synchronization from external input

When an asynchronous clock or an asynchronous signal is input, the clock is converted to an enabling clock. This method is the same as the previous section on edge detection.

(4) Optimal Design Scheme for system synchronization Signals

When FPGA is powered on for a short period of time, it takes more or less time for all logic blocks to be powered on (although very short ). In projects with low time series requirements, it may seem negligible. However, the FPGA is quite unstable when dozens of NS or MS are powered on. Therefore, when synchronizing asynchronous signals, the entire system will be delayed for a certain period of time, and more stable running results will be obtained to a certain extent. At the same time, after processing, the FPGA is actually working after the system is powered on stably, so the corresponding logic sequence is more stable and accurate.

The following are solutions to the problems encountered by bingo in actual projects. After processing the system with a latency of MS, the system that was originally prone to errors did not experience any exceptions.

The following is the specific example of the Code:

/*************************************** ************

* Module name: synchronism_pll_delay_design.v

* Engineer: crazy bingo

* Target device: ep2c8q208c8

* Tool versions: Quartus II 11.0

* Create Date: 2011-6-25

* Revision: V1.0

* Description:

**************************************** ************/

Module synchronism_pll_delay_design

(

Input CLK, // 50 MHz

Input rst_n, // global Reset

Output sys_rst_n, // system reset

Output clk_c0 // 50 MHz

);

//----------------------------------------------

// Rst_n synchronism, is controlled by the input CLK

Reg rst_nr1, rst_nr2;

Always @ (posedge CLK or negedge rst_n)

Begin

If (! Rst_n)

Begin

Rst_nr1 <= 1 'b0;

Rst_nr2 <= 1 'b0;

End

Else

Begin

Rst_nr1 <= 1 'b1;

Rst_nr2 <= rst_nr1;

End

End

//----------------------------------

// Component instantiation for system_delay

Wire delay_ OK;

System_delay system_delay_inst

(

. CLK (CLK ),

. Delay_ OK (delay_ OK)

);

Wire pll_rst = ~ Rst_nr2 &~ Delay_ OK; // active high

//----------------------------------------------

// Component instantiation

PLL

(

. Areset (pll_rst ),

. Inclk0 (CLK ),

. C0 (clk_c0 ),

. Locked (locked)

);

//----------------------------------------------

// Sys_rst_n synchronism, is control by the highest output CLK

Wire locked;

Wire sysrst_nr0 = rst_nr2 & locked & delay_ OK;

Reg sysrst_nr1, sysrst_nr2;

Always @ (posedge clk_c0 or negedge sysrst_nr0)

Begin

If (! Sysrst_nr0)

Begin

Sysrst_nr1 <= 1 'b0;

Sysrst_nr2 <= 1 'b0;

End

Else

Begin

Sysrst_nr1 <= 1 'b1;

Sysrst_nr2 <= sysrst_nr1;

End

End

Assign sys_rst_n = sysrst_nr2; // active low

Endmodule

//###################################### ##########//

//###################################### ##########//

Module system_delay

(

Input CLK, // 50 MHz

Output delay_ OK

);

//------------------------------------------

// Delay 100 ms for steady state

Reg [22: 0] CNT;

Always @ (posedge CLK)

Begin

If (CNT <23 'd50 _ 00000) // 100 ms

CNT <= CNT + 1' B1;

Else

CNT <= CNT;

End

//------------------------------------------

// Sys_rst_n Synchronism

Assign delay_ OK = (CNT = 23 'd50 _ 00000 )? 1 'b1: 1' B0;

Endmodule

The RTL us ii rtl diagram is as follows: