Chapter II: Location of the SystemVerilog declaration

1.package definition and import definition from package (* * *)

In Verilog, declarations for variables, lines, tasks, and function must be between module and Endmodule. What if a task is referenced by more than one module?

Verilog with include solution, SystemVerilog borrow VHDL package solution.

@1:package can contain an integrated structure that:

1.parameter and Localparam Constants Definitions

2.const variable definition

3.TYPEDEF user-defined type

4. Automatic task and function definition

5.import statements

6. Operator overloading Definitions

Eg:package definition;

Parameter VERSION = "1.1";

typedef ENUM{ADD,SUB,MUL} opcodes_t;

typedef struct{

logic [31:0]a,b;

opcodes_t opcode;

}instruction_t;

function automatic [31:0] Multipler (INPUT[31:0]A,B);

return a*b;

Endfunction

Endpackage

@2:package Content Reference Method:

1. Use range Operator::

Module ALU (Input definitions::instruction_t IW, input logic clock, output logic [31:0] result);

ALWAYS_FF @ (Posedge clock) begin

Case (Iw.opcode)

Definitions::add:result = IW.A + iw.b;

Definitions::sub:result = iw.a–iw.b;

Definitions::mul:result = Definitions::multiplier (IW.A, iw.b);

Endcase

End

Endmodule

2.import Statement Import a specific subkey into a module or an access port

Module ALU (Input definitions::instruction_t IW, input logic clock, output logic [31:0] result);

Import Definitions::add;

Import Definitions::sub;

Import Definitions::mul;

Import Definitions::multiplier;

ALWAYS_FF @ (Posedge clock) begin

Case (Iw.opcode)

Add:result = IW.A + iw.b;

Sub:result = iw.a–iw.b;

Mul:result = Multiplier (IW.A, iw.b);

Endcase

End//import definitions::opcodes_t;?

Endmodule

3.import Statement wildcard import into a module or an access port

Module ALU (Input definitions::instruction_t IW, input logic clock, output logic [31:0] result);

Import definitions::*;

Always_comb begin case (Iw.opcode)

Add:result = IW.A + iw.b;

Sub:result = iw.a–iw.b;

Mul:result = Multiplier (IW.A, iw.b);

Endcase

End

Endmodule

wildcard import does not automatically import the entire package, just the equivalent of adding a search path!!

4. Import the subkey into the

Import definitions:: instruction_t;

Module ALU (Input instruction_t IW, input logic clock; output logic [31:0] result);

The package can also be imported into a domain with a wildcard character. Wildcard import simply adds the package to the SystemVerilog source path!!

2. $unit compile the declaration space

Do not make any claims in the space of the "no", all shared claims are in the package.

When needed, you can import the package into the *.

The statement is too scattered, the structure is disorderly, the logic is bad, not conducive to debugging.

3. Declarations in unnamed blocks

After a block is named, it can be layered to refer to variables, but it cannot be synthesized.

4. Enhanced Time Unit definition

1. Time value containing the time unit:

Forever #5ns Clock = ~clock; There can be no space between the time value and the unit!!

2. Use keywords Timeunit and timeprecision:

Module adder (input wire[63:0] A, B, output reg [63:0] sum, output reg carry);

Timeunit 1ns;

Timeprecision 10ps;//is part of the module,

...//rather than as a software tool directive

Endmodule

Timeunit and Timeprecision bind the module, interface, or program block directly to the time unit and precision information,

It solves the uncertainty of timescale and its dependence on file order.

It must precede any other declaration or statement, immediately following the declaration of the module, interface, or program.

The declarations of timeunit and timeprecision can be in the compilation unit domain, but must precede other declarations.

Chapter II: Location of the SystemVerilog declaration