Clock gate [Post]

Clock gate, English name gate clock. The so-called "door-control" refers to the logical output of one clock signal and another non-clock signal. For example, you use a control signal "and" CLK "to control the CLK's effective time.
This is used in ASIC to reduce power consumption, because the power consumption is mainly caused by the switching of MOS, and the output of the gate clock remains unchanged for a period of time, reducing power consumption; however, in FPGA, clock passing through a dedicated network may cause many problems, such as glitch, skew, jitter, and timing analysis. Therefore, in FPGA design, do not use a clock gate.

An array clock is usually used to form a gate clock. The clock gate is often related to the microprocessor interface and uses the address line to control the write pulse. However, every time you use a combined function clock trigger, there is usually a clock gate. If the following conditions are met, the clock can work as reliably as the global clock:
1. The logic for driving the clock must only contain one "and" door or one "or" door. If any additional token is used in some working conditions, a glitch is generated by competition.
2. One input of a logic gate is used as the actual clock, and all other inputs of the logic gate must be used as the address or control line. They comply with the time constraints related to clock establishment and holding.
We can usually convert the clock to a global clock to improve the reliability of the design project.

 

 

 

Generally, the logic that drives the gate clock only contains one door. If there are other additional logic, it is easy to generate unwanted glitch due to competition. When a clock is switched, the clock can be controlled by signal. When the system does not work, you can turn off the clock and the entire system is in an inactive state, which can reduce the power consumption of the system to some extent.

However, the use of the clock gate does not conform to the idea of synchronous design. It may affect the implementation and verification of the design. From a functional perspective, using the Enable clock to replace the clock is a good choice. However, when the Enable clock is disabled, the clock signal is still working, it cannot reduce the power consumption of the system as the Clock.

Altera's solution:

For the system clock CLK that is effective in the rising edge, the descent edge first beats the clock, and then uses the enable signal and the CLK phase of the system clock as the clock of the subsequent circuit.

Such a clock-gate circuit solves some common problems of the combined logic. It avoids burrs and effectively limits the potential harm of sub-steady state. However, from another perspective, if the designed system's clock duty cycle is not very stable, or the output enable and CLK logic is too complex, it also brings about some functional and timing problems. In general, as long as the designer controls the clock duty cycle and logic complexity in the design, it is more feasible than the following simple clock gate circuit scheme.

Clock gate [Post]