Clock Sense and Analysis mode

Primetime automatically track the inverter and buffer in the clock tree to get the clock sense for each register.

If the clock tree is only buffer and inverter, the clock signal that arrives at the register clock can be represented as "unate".

Positive unate:rising Edge's clock source causes the register clock pin to rising edge.

Negative unate:rising Edge's clock source causes the register clock pin to falling edge.

The clock does not appear unate:

Primetime that the output of the pulse generator is not unate.

In Non-unate's clock network, you can set the sense of the clock that needs to be analyzed by command set_clock_sense.

If you use this command for a unate clock, primetime generates an error when the sense is inconsistent with the actual sense.

Set_clock_sense-positive-clock [Get_clocks CLK] [get_pins mux1.z]

-clock to specify the clock on the pin, there may be more than one clock source on a pin.

Set_clock_sense-stop_propagation indicates that the clock does not propagate on the physically.

Set_clock_sense-logical_stop_propagation indicates that clock may continue to be propagate as data, but not as

Clock for analysis.

Set_clock_sense-logical_stop_propagation-clocks CLK u3/a

Pulse clock: Some short pulse, its rising and falling edge are trigger by the same edge of a clock.

The definition of pulse clock can be determined by a pulse generator cell/create_generated_clock/set_clock_sense

-edge {1 1 3} indicates that the first rising and falling edges are 1 moments, and 3 is the next rising edge.

In semiconductor devices, Process/temperature/voltage has a significant impact on device performance, and in primetime, commands

Set_operating_conditions to set operate condition.

Three kinds of analysis mode provided by primetime;

1) Single operating mode,

2) best-case/worst-case mode, for setup check, use maximum delay path, for hold check, use minimum delay path

3) On-chip-varient mode allows different pvt (operating mode) to be used for setup and hold check on the same path

For setup Mode,launch clock and data use Max Delay,capture clock with min delay.

For hold mode,launch clock and data use min delay,capture clock to use Max delay.

In a minimum-maximum analysis, the value of this minimum and maximum can be:

1) Input and Output external delays

2) Port wire load model/net wire load model

3) Delays annotated form standard Delay Format (SDF)

4) Port fanout number

5) Net Capacitance/resistance

6) Clock latency and clock transition time

7) Input Port driving cell

When calculating maximum, PT uses longest path, worst-case operating conditions, longest transition times, maximum cell delays

Net delay value can be identified directly through two SDF files, or the PT can be computed based on different operating condition.

Set_operating_conditions-analysis_type on_chip_variation-min Best-max Worst

Report_timing-delay_type min

Report_timing-delay_type Max

Clock Sense and Analysis mode