Close the MMU and cache

Processor internal registers, the fastest access, but the number of small

TCM: Tightly coupled memory (Cache, main memory)

Secondary memory (Flash, SD, etc.)

Cache is a small, but very fast-access memory

It keeps a copy of the data in the most recently used memory,

The cache is transparent, and he automatically decides which

data, and what data is overwritten. According to the function division:

I-cache: Instruction Cache

D-cache: Data cache

Virtual Address: The address used in the program

Physical Address: The actual address of the physical storage unit

Virtual addresses can resolve address conflicts, which can be a process that uses more space

1, make Icache+dcache invalid

2. Close I/d-cache

. Text.global _start_start:b Reset Ldr pc, _undefined_instruction ldr pc, _software_interrupt ldr pc, _prefetch_abort ldr pc, _da Ta_abort Ldr pc, _not_used ldr pc, _irq ldr pc, _fiq_undefined_instruction:. Word undefined_instruction_software_interrupt:. Word software_interrupt_prefetch_abort:. Word prefetch_abort_data_abort:. Word data_abort_not_used:. Word not_used_IRQ:. Word IRQ_fiq:. Word Fiqundefined_instruction:    NOP    Software_interrupt:    NOPPrefetch_abort:    NOP    Data_abort:    NOP    not_used:    NOP    IRQ:    NOP    Fiq:    NOPReset:bl set_svc bl disable_watchdog bl diasble_interrupt bl Disable_mmumovpc, LRset_svc:Mrs R0, CPSR Bic r0, R0, #0x1f Orr r0, R0, #0xd3 msr cpsr, R0movpc, Lr#define pwtcon 0x53000000Disable_watchdog:Ldr R0, =pwtconmovR1, #0x0StrR1, [R0]movpc, Lrdisable_interrupt mvn R1, #0x0 ldr r0, =0x4a000008StrR1,[r0]movpc, LR disable_mmu mcr P15,  0, R0,c7,c7,0  MRC P15,0, r0,c1,c0,0  Bic r0,r0,# 0x00000007 MCR P15,0, r0,c1,c0,0mov pc, LR    

Close the MMU and cache