Common ARM Assembly Instructions

Common ARM Assembly Instructions

[Date: 2012-07-14]

Source: Linux Community xuyuanfan77

[Font: Big Small]

In embedded development, assembler is often used in very critical places, such as the initialization of the system at startup, environmental protection when entering or leaving the interrupt, and the performance requirements of the recovery.

The arm instruction set can be divided into six categories, namely data processing instruction, Load/store instruction, jump instruction, program status register processing instruction, coprocessor instruction and exception generating instruction.
The basic format used by ARM directives is as follows:
〈opcode〉{〈cond〉}{s}〈rd〉,〈rn〉{,〈operand2〉}
OpCode operation code, instruction mnemonic, such as LDR, STR, etc.
Cond optional conditional code; Execution conditions, such as EQ, NE, etc.
s optional suffix; If "s" is specified, the condition code in CPSR is updated according to the instruction execution result.
Rd Target registers.
Rn holds the register of the 1th operand.
Operand2 number of 2nd operand

Arm is addressed in the following ways:
Immediate addressing
Register addressing
Register Indirect Addressing
Base Address plus offset address
Stack addressing
Block Copy Addressing
Relative addressing
This is not a detailed description and can be found in the relevant documentation.

Data processing Instructions
Load/store directive
Transfer instructions between the program status register and the general register
Transfer instructions
Exception Interrupt Instruction
coprocessor directives


A detailed description of the various assembly instructions is provided in the data sheets of s3c2410 and s3c2440;
1. Relative Jump instruction: B, BL
The difference between the two directives is that the BL instruction stores the return address (the address of the next instruction of BL) in the LR register in addition to the jump.
The jump range for these two instructions is 32M before and after the current instruction.

b Funa
....
Funa:
b Funb
....
FUNB:
....

2. Data transmission instruction MOV, address read pseudo instruction Ldr
The MOV instruction can assign the value of a register to another register, or assign a constant to the register.
MOV r1, R2
/* above is R1 = r2*/
mov r1, #1024
/*R1 = 1024*/

The constants transmitted by MOV must be represented by an immediate number. You can use the LDR command to assign a value when you cannot represent it in an immediate number.
LDR is a pseudo-command, not a real-world instruction, and the compiler expands it into a real instruction, and if the constant can be represented by an "immediate number", the MOV instruction is used, otherwise the constant is stored in a location at compile time and read out using a memory read instruction.
LDR R1, = 1024
/*R1 = 1024*/

3. Memory Access instruction LDR, str, LDM, STM
LDR can refer to either as low as read pseudo-instruction or as a memory access instruction. When the second parameter is preceded by a ' = ' mark pseudo-instruction, otherwise the table memory Access instruction.
The LDR instruction reads the data from memory to the register, and the str instruction stores the registers in memory, and their operands are 32-bit.

LDR R1, [R2, #4]/* Reads memory unit data with address r2+4 to R1 */
LDR R1,[R2]/* Read memory unit data with address R2 to R1 */
Ldr R1,[R2], #4/* Read memory unit data with address R2 to R1, and then r2=r2+4*/
STR R1, [R2, #4]/* Save the R1 data to a memory unit with an address of r2+4 */
STR R1, [r2]/* .... */
STR R1, [R2], #4/* Save the R1 data to a memory unit with an address of R2, then r2= r2+4*/

A multi-register transfer instruction can store any subcollections (or all) of 16 visible registers (or all) in memory or read data from memory into the collection of registers with a single instruction (R0~R15). Multi-register data access is available with more limited addressing modes than single-register access directives. The assembly format for multi-register access directives is as follows:

Ldm/stm{<cond>}<add mode> rn{!}, <registers>

4, add minus instruction add, sub

Add R1, R2, #1/*r1=r2+1*/
Sub R1, R2, #1/*r1=r2-1*/

5, the program status register access instruction Msr,mrs

The ARM directive has two instructions for transferring data between the status register and the General register. Modifying the status register is typically done through the three-step "read-Modify-write-back" operation. These two instructions are:
Transfer instruction (MRS) of the status register to the Universal register
Universal register to Status register transfer instruction (MSR)

Its assembly format is as follows:
Mrs{<cond>} rd,cpsr| SPSR
Its assembly format is as follows:
Msr{<cond>} cpsr_f | Spsr_f,#<32-bit immediate>
Msr{<cond>} cpsr_<field> | Spsr_<field>,rm

MSR CPSR, r0/* copy R0 to CPSR */
Mrs R0, CPSR/* Copy CPSR to R0 */

6. Abnormal interrupt Instruction
The exception interrupt instruction can be divided into two types:
Software interrupt instruction (SWI)
Breakpoint Instruction (bkpt-only for v5t system)
The software interrupt instruction SWI is used to generate a SWI exception interrupt, which is used to implement the call of the program in user mode to the privileged mode in the operating system; Breakpoint interrupt instruction Bkpt is mainly used to generate software breakpoints for debugging programs.

7. Other pseudo-directives

. extern Main
. text
. Global _start
_start:

'. extern ' defines an external symbol (which can be a variable or a function), and the code above indicates that main referenced in the table text file is an external function.

'. Text ' means that the following statements are part of the code snippet

'. Global ' defines a program label in this file as global, such as ' _start ' is a global function

Common ARM Assembly Instructions