Common frequency Crossover

Module Fenpin #
(Parameter n=25000_000)
(CLK,CLR,CLK0,CLK1,CLK2,CLK3,CLK4);
Input clk,clr;
Output CLK0,CLK1,CLK2,CLK3,CLK4;
Reg CLK0,CLK1,CLK2,CLK3,CLK4;
REG[12:0] Cnter0;
REG[4:0] Cnter1,cnter2,cnter3,cnter4;
[Email protected] (Posedge CLK or Negedge CLR)
if (~CLR)
cnter0<=0;
Else
if (cnter0==n-1)
Begin
cnter0<=0; Clk0<=1 ' B1;
End
Else
Begin
cnter0<=cnter0+1; clk0<=0;//10k
End

[Email protected] (Posedge clk0 or Negedge CLR)
if (~CLR)
cnter1<=0;
Else
if (cnter1==9)
Begin
cnter1<=0; Clk1<=1 ' B1;
End
Else
Begin
cnter1<=cnter1+1;clk1<=0;//1k
End
[Email protected] (Posedge clk1 or Negedge CLR)
if (~CLR)
cnter2<=0;
Else
if (cnter2==9)
Begin
cnter2<=0; Clk2<=1 ' B1;
End
Else
Begin
cnter2<=cnter2+1;clk2<=0;//100
End
[Email protected] (Posedge clk2 or Negedge CLR)
if (~CLR)
cnter3<=0;
Else
if (cnter3==9)
Begin
cnter3<=0; Clk3<=1 ' B1;
End
Else
Begin
Cnter3<=cnter3+1;clk3<=0;//10
End
[Email protected] (Posedge clk3 or Negedge CLR)
if (~CLR)
cnter4<=0;
Else
if (cnter4==9)
Begin
cnter4<=0; Clk4<=1 ' B1;
End
Else
Begin
Cnter4<=cnter4+1;clk4<=0;//1
End
Endmodule

Common frequency Crossover