Communication between the core of the baseband processor and the application processor

The current mobile phone architecture uses a variety of communication methods between processors. Currently, the popular interfaces of split AP and CP include SPI, I2C, UART, USB, and dual-port interconnection, shared Memory is used in the SOC mode. The control commands are transmitted between the baseband processor and the AP processor in the message format to complete functions such as calls, short messages, and mobile Internet access. The communication protocols include traditional AT commands and mbim. Generally, the chip supports multiple interfaces and designs a general software driver platform driver.

1. gpio: General purpose input/output)

Gpio provides additional control and monitoring functions when the microcontroller or chipset does not have enough I/O ports or when the system requires remote serial communication or control. For example, when a call is made, the AP uses gpio to wake up the bp, and when the call is made, the AP also uses gpio to wake up the AP.

2. UART: Universal Asynchronous Receiver/Transmitter)

UART is used for asynchronous communication and bidirectional communication to realize full-duplex transmission and reception. Its typical data transmission rate is about 1.5 Mbps, while high-speed UART supports a rate of up to 5 Mbps. This data transmission rate still cannot meet the communication requirements between high-bandwidth processors. physical interactions (data transmission, at command, etc.) between chips in 2G networks can be achieved through UART.

3, I2C: Inter-Integrated Circuit

The I2C bus is a universal equipment bus that transmits clock signals and bidirectional data signals. The transmission process is controlled by I2C protocol. although the latest I2C specification proposes a high-speed mode with a throughput of up to Mbps, most currently available devices can only support data transmission rates from Kbps to 1 Mbps.

4. spi: serial peripheral interface)

The SPI supports data transmission rates of over 20 Mbps, but it does not have a unified specification. Therefore, it mainly depends on what kind of processor is used. If a baseband processor is used, SPI generally supports a data transmission rate of about 16 Mbps. As many baseband processor manufacturers have released their own patented products, different SPI interfaces on different baseband processors pose different challenges to designers, making it difficult to pair two different baseband processors, to achieve the best SPI speed.

5. USB: Universal Serial Bus)

A popular interconnection technology is the Universal Serial Bus (USB) interface. Most processors have full speed USB (FS-USB) performance, the maximum data transmission rate of the FS-USB is 12 Mbps, because the USB protocol itself has a high packet overhead, so its actual throughput is about 6 Mbps. USB 2.0 can meet the speed requirements of edge, can meet the speed requirements of 3G, HSPA, but the USB scheme requires that the baseband processor must have a USB interface, the application processor can support USB host or usb otg devices, software processing is relatively complex and the USB power consumption is relatively high because the USB Host remains working even when data is not transferred (the USB-ULPI/HSIC interface reduces power consumption ).

6. dual-port Interconnection

The data transmission rate of the blank port technology is getting higher and higher, and the LTE downlink speed can reach Gbit. Therefore, although the focus is on improving the processor capability and wireless data transmission rate, inter-processor communication has always been a major bottleneck. As mobile phone technology becomes increasingly complex, the amount of data transmitted between processors will certainly increase. A potential solution to the problem of inter-processor interconnection is the adoption of multi-port interconnection technology-buffer multi-port devices as the interconnection mechanism between two CPUs, can support high-speed data transmission between the two, it also helps reduce the power consumption of Inter-Processor Communication (IPC.

The access time of the dual-port memory is only 40 ns, and the data transmission speed is up to Mbps. The multi-port solution supports passive communication between processors. Because the multi-port interconnect mechanism serves as a buffer, the receiver's processor can stay in sleep mode when receiving the multi-port interconnect interruption, and only enters the working state when receiving data, thus reducing power consumption.

Figure 1 Comparison of Inter-core communication technologies

7. Single-Chip sharememory: Memory Sharing

when all core cores are integrated into a single core, the division of labor between AP and BP is still clear, the communication between the two can rely on Memory sharing to quickly and effectively solve the problem of inter-Processor Communication (Data Exchange), which has a great advantage for big data transmission, however, the technical difficulty is complicated.