Comparison between Synchronous Reset and Asynchronous Reset

Comparison between Synchronous Reset and Asynchronous Reset I. features:

Synchronous Reset: Synchronous Reset means that the reset signal is valid only when the clock rising edge is reached. Otherwise, the system cannot be reset. It is described as follows in the format of "
always @ (posedge CLK) Begin
If (! Rst_n)
...
end
Asynchronous Reset: whether or not the clock edge arrives, as long as the reset signal is valid, reset the system. It is described in the following example using the Tilde:
always @ (posedge CLK or negedge rst_n) Begin
If (! Rst_n)
...
end
2. Advantages and Disadvantages: 1. In general, there are about three advantages of Synchronous Reset:
A. It is conducive to the simulation of the simulator.
B. The designed system can be used as a 100% synchronous time series circuit, which greatly facilitates Time Series Analysis and generally leads to a high FMAX.
C. Because it is valid only when the clock effective level is reached, it can filter out burrs higher than the clock frequency. There are also many disadvantages, mainly including the following:
A. The effective duration of the reset signal must be greater than the clock cycle to be truly recognized and reset tasks can be completed by the system. Also consider factors such as CLK skew, combined logical path Delay, and reset delay.
B. Because DFF in the target database of most logical devices only has an Asynchronous Reset port, if Synchronous Reset is used, the synthesizer inserts the combined logic into the data input port of the Register, which consumes a lot of logical resources.

2. For Asynchronous resetting, there are also three advantages that correspond to each other.
A. DFF of most target device libraries has Asynchronous Reset ports. Therefore, Asynchronous Reset can save resources.
B. Relatively simple design.
C. Asynchronous Reset Signal Identification is convenient, and FPGA global reset port GSR can be easily used.

Disadvantages:
A. problems may occur when the reset signal is released (release. Specifically, if the reset release is near the effective clock edge, it is easy to make the Register output appear in the sub-steady state, resulting in the sub-steady state.
B. Reset signals are susceptible to glitches.
Iii. Summary:
Therefore, Asynchronous Reset and synchronous release are generally recommended, and the reset signal is effective at a low level. In this way, you can have the best of both worlds.