Comprehensive Analysis of the paging mechanism in chapter 3 of "writing an operating system by yourself"

"Write the operating system yourself" read Sense http://blog.csdn.net/zgh1988/article/details/7059936

Comprehensive analysis of the first chapter of "self-writing Operating System" http://blog.csdn.net/zgh1988/article/details/7060032

Comprehensive Analysis of the "self-writing Operating System" Chapter 2 http://blog.csdn.net/zgh1988/article/details/7062065

Comprehensive Analysis of the "hands-on writing Operating System" Chapter 3 1 http://blog.csdn.net/zgh1988/article/details/7098981

Comprehensive Analysis of "writing an operating system by yourself"-"Real mode-protection mode-real mode"
Http://write.blog.csdn.net/postedit/7256254

Comprehensive Analysis of the "hands-on writing the Operating System" -- stack segment of the work mode http://blog.csdn.net/zgh1988/article/details/7256254

Comprehensive Analysis of "write your own Operating System"-jump rules between privileged-level code segments and different privileged-level code segments
Http://blog.csdn.net/zgh1988/article/details/7262901

 

Next I will use pmtest6.asm to describe the paging mechanism in protected mode.

1. Logical Address, linear address, and physical address

2. Paging Management Mechanism

3. PVDF, PTE, and S3.

4. The page chart after the pmtest6.asm initialization page Directory table and page table

5. How to determine the number of page tables based on the physical memory

I. Logical Address, linear address, physical address 1. What if the paging mechanism is not enabled?

 

 

2. When the paging mechanism is enabled?

 

Ii. Paging Management Mechanism

Next I will introduce how to convert a linear address to a physical address through the paging management mechanism.

 

The conversion uses a two-level page table. The first level is called the page Directory, which is 4 kb in size and stored in a physical page. Each table item is 4 bytes long and has a total of 1024 table items. Each table item corresponds to a page table at Level 2, and each page table at Level 2 also has 1024 table items. Each table item corresponds to a physical page. The table items in the page Directory table are referred to as page directory entry, and the table items in the page table are referred to as page table entry ).

 

Conversion process: 1) First, the page table is obtained from the page directory specified by register S3.

2) In the page table, obtain the physical top address based on the 12-21 digits of the linear address.

3) add the first address and the low 12 digits of the linear address to obtain the physical address.

Iii. PDP, PTE, and S3.

The structure of the partial code is as follows:

 

The structure of Pte is as follows:

The following figure shows the structure of c303:

The 20-bit-height ratio in is the 20-bit-height ratio of the first address of the page Directory table, the 20-bit-height ratio of the partial key is the first address of the page table, and the 20-bit-height ratio of the Pte is the first address of the physical page. In the protection mode, the addressing range is 0-4 GB. Why are these addresses stored in 20 bits?

The 20-bit-height ratio in is the 20-bit-height ratio of the first address of the page Directory table. The 12-bit-height ratio of the first address of the page Directory table is 0, this ensures that the page Directory table is 4 kb aligned. Similarly, the base address of the page table (page-Table Base Address) and the base address of the physical page (page base address) in the PTE are also 4 kb aligned page tables and pages with a height of 20 bits.

Iv. Page chart after pmtest6.asm initialization page Directory table and page table

Pagedirbaseequ200000h; page Directory start address: 2mpagetblbaseequ201000h; page table start address: 2 m + 4 K; enable the paging mechanism =============================================== =========== setuppaging :; for simplified processing, all linear addresses correspond to equal physical addresses. First, initialize the page directories mov ax, selectorpagedirmov es, axmov ECx, 1024xor EDI, edixor eax, eaxmov eax, pagetblbase | pg_p | pg_usu | pg_rww.1: stosdadd eax, 4096 loop. 1. Initialize all page tables mov ax, selectorpagetblmov es, axmov ECx, 1024 * 1024xor EDI, edixor eax, eaxmov eax, pg_p | pg_usu | pg_rww.2: stosdadd eax, 4096 loop. 2mov eax, pagedirbasemov 375, eaxmov eax, cr0or eax, 80000000 hmov Cr0, eaxjmp short. 3.3: nopret; after the paging mechanism is started, ================================================== ======

 

After the page Directory table and page table are initialized, you must first set the page Directory table to be directed to the page Directory table, and then set the PostgreSQL bit of Cr0.

5. How to determine the number of page tables based on the physical memory

Assuming that the total physical memory is 16 MB, the page Directory table and page table occupy 4 kb + 4 MB, but the page table only occupies 25% of the memory space. In fact, 16 MB memory only requires four page tables.

A physical page is 4 kb, and a page table contains 1024 PTE points to 1024 physical pages. Therefore, a page table points to a memory space of 4 kb * 1024 = 4 MB, therefore, 16 MB memory space requires only four page tables.

In this case, the page Directory table and page table only need to occupy 4 kb + 4*4 kb memory space.