Condition codes for ARM directives

1. Conditional flag bit for program status register

The B31 bit value of the result of the N operation. For signed twos complement, the result is negative when n=1, the result is positive or 0 o'clock n=0;

The result of the Z command is 0 o'clock Z=1, otherwise z=0;

C uses addition operations (including CMN directives), B31 bits produce c=1 when rounding, otherwise c=0. With subtraction operations (including CMP), the B31 bit generates borrow when c=0, otherwise c=1. For non-addition/subtraction instructions combined with the shift operation, C is the last b31 of the bit, and the other instruction C is usually the same;

V uses the addition/subtraction operation, v=1 when there is a sign overflow, otherwise v=0, the other instruction V is usually the same.

2. Each arm instruction contains a 4-bit condition code

Operation code	Condition Code mnemonics	Sign	Meaning
0000	EQ	Z=1	Equal
0001	NE (not Equal)	Z=0	Not equal
0010	CS/HS (Carry Set/high or Same)	C=1	Unsigned number greater than or equal to
0011	Cc/lo (Carry clear/lower)	C=0	Unsigned number less than
0100	MI (minus)	N=1	Negative
0101	PL (PLus)	N=0	Positive or 0
0110	VS (OVerflow Set)	V=1	Overflow
0111	VC (OVerflow Clear)	V=0	No overflow
1000	HI (High)	C=1,z=0	Unsigned number greater than
1001	LS (Lower or Same)	C=0,z=1	Unsigned number less than or equal to
1010	GE (Greater or Equal)	N=v	Signed number is greater than or equal to
1011	LT (less Than)	N!=v	Signed number is less than
1100	GT (Greater Than)	Z=0,n=v	Signed number is greater than
1101	LE (less or Equal)	Z=1,n!=v	Signed number is less than or equal to
1110	AL	Any	Unconditional Execution (default)
1111	NV	Any	Never Execute