Configuration of TMS320VC5402 I/O resources and communication with USB

Configuration of TMS320VC5402 I/O resources and communication with USB

[Date:]

Source: China Power Grid Author: Shan qiuyun, Li xingfei, Wang pan, State Key Laboratory of precision testing technology and instrument, Tianjin University

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0 Introduction

The DSP (Digital Signal Processor) chip TMS320VC5402 features high performance, low power consumption, and many resources. Its unique 6-bus Harvard structure enables it to work in six pipelines at the same time, the operating frequency is 100 MHz. It has two buffer serial port BSP, eight-bit Parallel EHPI (enhanced host interface), and programmable wait state generator, which can meet the requirements of data processing control.

In view of the large data volume, high speed requirements, and real-time control of the communication interface of this application system, this project uses high-speed USB (Universal Serial Bus) interface to achieve high-speed data processing and transmission. USB is a new type of interface technology. It is a bus standard for computer and peripheral device interface communication. It supports hot swapping, plug-and-play, and simple connection. This article describes the GPI () (I/0) resource configuration of VC5402 and the Slave (Slave) Slave 0 interface between CY7C68013 and peripherals.

1. System Principle

The system is based on the DsP of TI corporation, and consists of three parts: neural signal processing circuit, neural stimulation circuit and signal transmission circuit. The system first selects a path or multiple measurement points of the neural micro-electrode array based on the corresponding control signals to send the corresponding stimulus signals, and records the cell response while performing electrical stimulation on the brain cells, the collected neural signal data is transmitted to the host computer through USB port for pathological analysis, which realizes the control of electrical stimulation and high-speed real-time transmission and processing of brain signals. Based on the EEG database, the system can simulate and generate neural signals corresponding to motion, and conduct electrical stimulation on different brain regions to achieve the goal of treatment. System

Solution l.

In addition to the commonly used gpio in the VC54x series, TMS320VC5402 also provides users with multiple selectable GPIO: HPI 8 and McBSP. It can be used directly with various types of storage.

For the controller, choose Cypress's FX2 series product cY7C68013. EZUSB FX2 is an integrated microcontroller of the world's 1st USB processors produced by Cypress, including one 805l processor and one SIE (Serial Interface Engine) 1 USB transceiver, 8.5 kB On-chip RAM, 4 kB running 0 memory and 1 GPIF (Universal programmable Interface), bus standard transmission speed up to 480 Mbit/s, sufficient to meet the speed requirements of high-speed peripherals. Its structure 2 is shown in.

2 TMs320VC5402 I/o Resource Configuration

Because the system contains multiple processing modules, and at the same time, the neural micro-electrode array needs to select multiple channels for simultaneous neural electrical stimulation, signal acquisition and USB transmission. The GPIO resources of the DSP chip are insufficient. I/0 must be extended to meet the requirement. Therefore, this project configures EHPI as an 8-bit general I/O, and uses the data line to communicate with cY7C68013. Set McBSP to General I // 0 and use it as the control line of CY7C68013.

2.1. EHPI-8 for GPIO

The 8-bit EHPI of FMS320VC5402 sets the DSP to communicate with the main processor in the slave mode, so that both the host and DSP can access the DSP Memory. However, the 8-bit bidirectional data bus of HPI.8 can also be used as the GPIO pin. This function is valid only when the HPI-8 interface is disabled, that is, when the HPIENA pin is set to low power during the reset process. Two memory ing registers, GPIOCR (General Input/Output Control Register) and GPIOSR (General Input/Output Status Register), can be used to control the GPIO function of HPI.8 data pins.

The DIRx is used to set the HD0 ~ Whether HD7 is input or output. 3. The TOUTl output position of timer 1 is only valid for devices with two timers. It controls the timer l output to the HINT pin. When the system has only one timer, this bit is retained. When the HPI 8 interface is used, TOuTl bit and DIRx are forced to be set to zero, and the general input/output pins can only be in the input mode.

The GPIO pin (HDx, x = 0: 7) status can be monitored by the position in the GPIOSR. 4. When an HDx pin is set to the input end (by writing an "O" to the DIRx bit in GPIOCR "), the corresponding bits in GPIOSR can be read to determine the logical values detected on this pin. Similarly, when an HDx pin is set to an output end, the logic value driven to this pin is written in the corresponding position in GPIOCR.

To use HPI 8 Data pins as GPIO pins, you must first set these pins and then monitor or operate these pins by reading and writing GPIOSR.

2.2 McBSP used for GPIO

TMS320VC5402 is the first chip that introduced McBSP (Multi-Channel buffer serial port) in the 54x series. The serial port is established under the following two conditions (Serial Port pins CLKX, FSX, DX, CLKR, FSR, and DR can be used as GPIO pins instead of serial port pins ):

A) the relevant part of the serial port (sender or acceptor) is in the reset state, that is, the GPIO pin function of the relevant part of the serial port is enabled in SPCR [1, 2] B, (R/X) IOEN = l in PCR.

PcR (PIN Controller) describes how to configure the McBSP pin to a general I/0 pin bit, as shown in Figure 5.

Table l lists detailed configurations.

Taking Fs (R/x) as an example, Fs (R/x) M = 0 sets this pin as the input, while Fs (R/x) M = l, this pin is set as output. When FS (R/x) is configured as output, the value driven to the FS (R/x) PIN is the value stored in Fs (R/x) P. If Fs (R/x) is configured as input, Fs (R/x) P becomes a read-only bit, which reflects the status of the Fs (R/x) signal. Similarly, the CLK (R/x) PIN can be configured by CLK (R/X) M and CLK (R/x) P.

DX is always used as the output. When the sending end is selected as the GPIO pin, the DX-STA3 and bit values in the PCR are driven to DX; DR is always used as the input, and its value is stored in the pcr dr. STAT bit; because the total number of cLXS is used as the input of McBSP and affects sending and receiving operations, to configure CIXS as a general input pin, the sender and acceptor must both be in the reset State and (R/x) IOEN = l.

3 CY7C68013 and tms320vcl5402 hardware connection

The connection method between CY7C68013 and DSP is Master/Slave interface: programmable interface GPIF and Slave FIFO. The programmable interface GPIF is a host mode that allows you to write the read/write control sequence by software. It is flexible and convenient. It can be seamlessly connected to controllers, memories, and bus of almost all 8/16-bit interfaces.

The slave/slave mode is the slave mode. The external controller can read and write multiple buffers in fx2 just like a common FIFO mode. The Slave FIFO interface can also be flexibly configured to meet different needs.

This solution uses the FIFO mode, asynchronous read/write, and slave mode. Figure 6 shows the hardware connection between CY7C68013 and rms320c5402.

Flaga, flagb, and l fiagc indicate the status of the internal FIFO of c68013, vc5402 uses the MCB-SP port configured as the general I/O port to obtain the status information of the first-in-first-out (FIFO) instance, such as null, semi-full, and full, complete the read/write control for cytc68013. Vc5402 packet submission is implemented by a EHPI-8 port configured as a general I/O. The working process is as follows: when the DSP sends data to the PC through USB, it first checks three status signals: blank, half full, and full, and then writes the appropriate size of data to the USB to ensure that the data will not overflow. When the PC sends a command word to the DSP via USB, the USB notifies the DSP to read the command word in interrupted mode. Because the USB2.0 Sb Port D + and D are in high-speed mode of USB2.0, 15 kΩ is used on the first line, and the resistor is connected to the 3.3 V power supply.

4 USB 2.o Software Design

The USB software includes three aspects: Firmware design, driver design, and host application design.

4.1 Firmware Design

Firmware is a program running on the USB 2nd bus controller. It has the following functions: Chip initialization; processing USB standard device requests; and completing enumerations of Interface Devices with host drivers after loading; data exchange with TMS320VC5402; data exchange with the USB interface between the host.

Cypress provides the fx2 chip with a Firmware Library (ezusb.1ib) and a framework (Frame Work) developed based on Keil C51 ). With these firmware architectures, the main task of user development is to modify periph. C based on custom devices. In this system, CY7C68013 receives and processes USB driver requests and uploads data to the PC in real time. In this solution, CY7C68013 is used in asynchronous Slave FIFO mode. Map the 4 kb FIFO to two endpoints, that is, the End-Point2 and endpoint6, the corresponding register operation is: ep2cfg = oxa0, ep6cfg = 0xe2. : Endpoint2 and endpoint6 correspond to the internal FIFO of 2 kb respectively), used to store the data that lisb needs to upload and accept. Endpoint2 is out. Type, receiving data from the host; endpoint6 is in type, send data to the host. The corresponding register operation is ep21_ocfg = 0xl L, and ep6 slave ocfg = 0x0d. Set endpoint2 and end. point6 to Automatic bulk transmission

Method, that is, the CY7C68013 8051 kernel is not required during data transmission. This method is the most commonly used transmission mode, which features data reliability and high transmission rate compared with other USB2.0 defined transmission modes. Therefore, you do not need to add code to the User Function TD-Poll () in periph. C, but only set the chip working mode in the TD-lnit () function. To improve the overall lisb transmission function and improve firmware robustness, flfo is added with the automatic reset function.

4.2 Driver Design

The USB driver contains the USB bus driver and USB device driver. The USB bus driver is provided by the Windows operating system (usbd. sys), the user does not need to know the work details of the USB bus driver; the USB device driver is located on top of the USB bus driver, you can send or receive information about a USB device by sending an IRP containing a USB request to the USB bus driver. The USB driver can use the general driver provided in the CY7C68013 development kit, which can be used directly after being compiled by DDK without modification. It is provided by Cypress to facilitate user development of the ijsb interface [7].

4.3 host Application Design

In the system, the main tasks of host applications are to read the processed data from the DSP at a high speed, store the data, display the processing results, and send control commands to the DSP. VC ++ 6.0 is used for application development. Because the Development Board of EZ-USB fx2 provides a host-side driver, so in application development, you can directly call the win-dows API function to Win32 subsystem Win32 call, allows you to perform I/O operations on USB devices.

When the application is executed, it first uses createfile () to establish a connection with the peripheral device, so as to open the device driver and obtain the device handle. If the createfile () function returns a successful result, you can perform read and write operations on the device. Generally, readf, Ile, and writefile are used. Then, deviceioconlml () is called Based on the handle to complete data transmission. After the devi. celocontrol () function returns the result, the data is saved to the computer.

You can display and store data in the buffer zone. When the program needs to process multiple transactions, the interface should be opened asynchronously. Fx2 is multi-endpoint communication, but it can only be quasi-duplex communication. In this case, asynchronous communication can be used to coordinate program transactions.

Figure 7 uses the interface written in VC ++ 6. O to monitor data transmission during USB debugging.

5 conclusion

The system uses high-speed DSP as the main controller. Through the software and hardware design of CY7C68013 and the configuration of DSP's extended I/O port, the high-speed DSP system's USB2.0 interface is realized, it meets the requirements of high-speed EEG data collection and transmission. With the development of DSP technology, if a DSP with a higher frequency is used in the system, it can achieve faster operation and transmission. It is used for controlling information sources of prosthetic devices to Achieve flexible movements.