Considerations for Hardware Design of Blackfin Processors

 

Through the learning and understanding of the Blackfin Processor, the precautions for the hardware design of the processor are summarized for reference.

1. 5 V compatibility: The nonstandard 5 V voltage added to the signal may damage the device and cause a fault. The output end of the Blackfin Processor cannot be connected to the input end of the 5 V voltage device, the signal pins of most Blackfin processors are not compatible with 5 V voltage, but there are also exceptions, such as some dual-line interface signals (Twi ). If necessary, other signal pins of the processor need to use a level converter so that the voltage is less than or equal to the absolute maximum value specified in the processor data manual. The level converter is usually used for the can sending receiver and atapi interfaces. To prevent high voltage, only throttling resistors cannot provide adequate protection.

2. Signal Integrity: rapid increase and decrease of signals in intermittent communication faults are the primary cause of signal integrity problems. Different Blackfin processors have different edge rates. Similarly, some signals are more sensitive to noise and signal reflection. Therefore, only simple signal integrity analysis methods are used to prevent transmission line reflection and additional clock and synchronous signals are introduced. For the following signals, matching the short cabling length with the serial connection terminal is critical:

1) The clkin signal must be connected to a single impedance matching resistor in the drive end;

2) Sport serial port interface signals (tclk, rclk, RFS, and TFs) must be matched using terminals;

3). PPI signals, such as ppi_clk and synchronous signals, will also benefit from these standard signal integrity technologies;

4). SDRAM clock, control, address and data signals will also benefit from these series of terminals that reduce electromagnetic interference (EMI) matching.

3./Reset DRIVER: the input signal of most Blackfin processors is not lagging behind. Therefore, input signals that increase or decrease monotonically are required. Because the R/C delay circuit is sensitive to noise, the/reset signal should not be directly connected to the R/C delay circuit, and the/reset signal should be provided through a dedicated reset monitoring chip.

4. Bypass capacitor: When the processor operates at a higher speed, it is critical to add an appropriate bypass capacitor to the internal power supply pin. When working at high frequencies, the parasitic inductance and wiring that the capacitor hates will reduce the effectiveness of the bypass capacitor. When the processing speed is higher than MHz, it is necessary to take the following two measures. First, the capacitance must be physically small, and its lead should be very short to reduce the inductance. The capacitance of the 0402 package will have a better effect than the capacitance of the larger size. Second, the smaller capacitance value will increase the resonance frequency of the LC circuit. For vddint Power Supply filtering, although the 0.1 UF capacitor works well under 50 MHz, it is more suitable to use a combination of 0.01, 0.001, UF, or even pf capacitor in the MHz range.

5. The gpio port signal is used for input or output: during power-on reset, all common signals are input signals. However, some signals may change to output signals during the loading process, depending on the selected loading mode, such as hwait, which is an output signal in all loading modes. When an external device drives an output signal, the signal cannot be used as an input signal. If the hwait level is critical during boot loading, the signal cannot be used for output. After the reset, The gpio signal must be used as the output signal. You need to use the pull-up or drop-down resistor to determine its status. Here we mainly consider the output signal, including the device enabling signal (such as nand flash memory) and the communication handshake signal, such as hwait, uartxtx, uartxrts, and canxtx, and select the SPI, serial Twi, and all chip selection signals. Some general outputs can be used in 5 V State. For example, SDA and SCL are exposed in all working modes. These pins are listed in the Data Manual, it must be pulled up when used as a universal output. However, the compatibility of these signal pins limits the output speed of the signal.

6. Crystal input: in addition to the kernel clock cclk that is provided to the processor and the peripheral clock sclk, The Blackfin Processor also has other local clock domains, such as real-time clock, Ethernet, USB and mxvr. Like clkin and xtal, these clock fields can also be driven by crystals or external clocks. The external clock can be a square wave or a sine wave. If a sine wave is used, the voltage level must be between the minimum and maximum values limited by the Data Manual. Some peripheral xtal pins can also be driven by the clkbuf output signal of the processor. If an external clock is used instead of a crystal, the corresponding xtal output signal must be suspended. If a crystal is used, check the data manual and crystal characteristics and use the recommended serial or parallel resistor. It is also important not to overload small crystals. If no clock domain is used in the application, pull or drop down the clock input signal to prevent oscillation.