Considerations for using Verilog HDL language

1, Wire and Reg difference, the input and output is a line type, indicating the connection of hardware lines, to be assigned in the Always module needs the middle Reg variable, both through: Assign input/output =reg type intermediate variable
2, case of the default can be used after the empty statement, default:;
3, the combination of logic with blocking assignment (=, like C language, statement execution immediately after completion of assignment), the sequential circuit with a non-blocking assignment (<=, the module after the execution of the assignment).
4, always block precautions:
① do not assign a value to the same variable in multiple always blocks, and the sensitive signal table of the ②always block should include all sensitive information/input signals (i.e. the signal to the right of the equals sign), which can be resolved with "@ (*)";
③ should not include incomplete branch and incomplete output assignment;

5, the modification needs to have the whole meaning, changes a bit may affect the procedure the many contents, for example, when changes the number, should the all involved the number of digits change, including case;

6, the constraint file pin do not use more, or there will be errors (download the board needs);
7, the simulation needs to some variables to be assigned to the value, such as CLK Flip, the count must use initial to the Q to assign the initial value, etc.
8, begin and end a point to match;
9, always @ (*), always @ (Posedge CLK);

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Considerations for using Verilog HDL language