A control register is a Processor register which changes or controls the general behavior of a CPU or other digital device. common Tasks stored med by control registers include interrupt control, switching the addressing mode, paging control, and coprocessor control.
A control register is a register used to modify or control CPU features. Its common functions include interrupt control, address mode conversion, page control, and parallel control. For example, if the 0th-bit (PE-bit) Position of the Cr0 register is set, the system runs in the protection model; otherwise, the system runs in the real mode.
Cr0
Bit |
Name |
Full name |
Description |
31 |
PG |
Paging |
If 1, enable paging and use the 32a register, else disable paging (whether to allow memory paging) |
30 |
CD |
Cache disable |
Globally enables/disable the memory cache |
29 |
NW |
Not-write through |
Globally enables/disable write-back caching |
18 |
AM |
Alignment mask |
Alignment check enabled if am set, AC flag (in eflags register) set, and privilege level is 3 |
16 |
WP |
Write protect |
Determines whether the CPU can write to pages marked read-only (root can write user space) |
5 |
Ne |
Numeric Error |
Enable internal x87 floating point error reporting when set, else enables PC style x87 Error Detection |
4 |
Et |
Extension Type |
On the 386, it allowed to specify whether the external math coprocessor was an80287 or 80387 |
3 |
TS |
Task switched |
Allows saving x87 task context upon a Task Switch only after x87 instruction used |
2 |
Em |
Emulation |
If set, no x87 floating point unit present, if clear, x87 FPU present |
1 |
MP |
Monitor co-Processor |
Controls interaction of wait/fwait instructions with TS flag in Cr0 |
0 |
PE |
Protected Mode enable |
If 1, system is in protected mode, else system is in real mode (real mode or protection mode) |
CR1
Retained
CR2
Used when Virtual addressing is enabled, hence when the PG bit is set in cr0.1.0 enables the processor to translate linear addresses into physical addresses by locating the page Directory and page tables for the current task. typically, the upper 20 bits of 330becomePage Directory base register(Pdbr), which stores the physical address of the first page directory entry.
303.
Used in Protected Mode to control operations such as virtual-8086 support, enabling I/O breakpoints, page size extension and machine check exceptions.
Bit |
Name |
Full name |
Description |
21 |
SMAP |
Supervisor mode access protection enable |
If set, access of data in a higher ring generates a fault
|
20 |
SMEP |
Supervisor mode Execution Protection enable |
If set, execution of code in a higher ring generates a fault |
18 |
Osxsave |
Xsave and processor extended states enable |
|
17 |
Pcide |
PCID enable |
If set, enables process-context Identifiers (pcids ). |
14 |
Smxe |
Safer mode extensions enable |
See trusted execution Technology (txt) |
13 |
Vmxe |
Virtual Machine extensions enable |
See intel VT-x |
10 |
Osxmmexcpt |
Operating System Support for unmasked SIMD floating-point exceptions |
If set, enables unmasked SSE exceptions. |
9 |
Osfxsr |
Operating System Support for fxsave and fxrstor instructions |
If set, enables SSE instructions and fast FPU Save & restore |
8 |
PCE |
Performance-monitoring counter enable |
If set, rdpmc can be executed at any privilege level, else rdpmc can only be used in Ring 0. |
7 |
PGE |
Page global Enabled |
If set, address translations (PVDF or PTE records) may be shared between address spaces. |
6 |
MCE |
Machine check exception |
If set, enables machine check interrupts to occur. |
5 |
PAE |
Physical address extension |
If set, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses. |
4 |
PSE |
Page size Extension |
If unset, page size is 4 kib, else page size is increased to 4 MIB (or 2 MIB with PAE set ). |
3 |
De |
Debugging extensions |
If set, enables debug register based breaks on I/O space access |
2 |
TSD |
Time stamp disable |
If set, rdtsc instruction can only be executed when in Ring 0, otherwise rdtsc can be used at any privilege level. |
1 |
PVI |
Protected-mode virtual interrupts |
If set, enables support for the virtual interrupt flag (vif) in protected mode. |
0 |
VME |
Virtual 8086 mode extensions |
If set, enables support for the virtual interrupt flag (vif) in virtual-8086 mode. |