Control registers and system address registers

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1. 1. Control Register
   1. Protection Control bit
   2. Coprocessor control bit
   3. Cr2 AND Cr 3
2. 2. system address register
   1. Global Descriptor Table register GDTR
   2. Local Descriptor Table register ldtr
   3. Interrupt Descriptor Table register idtr
   4. Task status segment register tr

 

80386 The following table lists the control registers and system address registers. They are used to control the way of work, control the implementation of the segmentation management mechanism and paging management mechanism.

Control System Register	CRX	Bit31	BIT30-BIT12	BIT11-BIT5	Bit4	Bit3	Bit2	Bit1	Bit0
	Cr0	PG	0000000000000000		Et	TS	Em	MP	PE
	CR1	Retained
	CR2	Page Fault linear address
	303.	Page Directory physical page number		000000000000

	BIT47-BIT16	BIT15-BIT0
Global Descriptor Table register GDTR	Base Address	Boundary
Interrupt Descriptor Table register idtr	Base Address	Boundary

BIT15-BIT0 Local Descriptor Table register ldtr Select Sub- Task status segment register tr Select Sub-

BIT31-BIT0 BIT31-BIT0 BIT11-BIT0 Base Address Boundary Attribute Base Address Boundary Attribute

<1> as shown in the preceding table, 80386 has four 32-bit control registers named Cr0, CR1, CR2, and C3. However, CR1 is retained for future development of processors. CR1 cannot be used in 80386; otherwise, invalid command operation exceptions may occur. Cr0 includes the control bit that shows how the processor works, including the control bit that enables and disables the paging management mechanism, and the control bit that controls the operation of the floating point coprocessor. Cr2 AND Cr 3 are used by the paging management mechanism. In Cr0, digits 5-30 and bits 0 to bits 11 are reserved bits. These bits cannot be random values and must be 0. The low 16-bit control register Cr0 is equivalent to 80286 of the machine status word MSW. 1. the bit 0 in the protection control bit control register Cr0 is marked with PE, and the bit 31 is marked with PG. These two bits control segment and paging management mechanisms, so they are called protection control bit. PE controls the segment management mechanism. Pe = 0, processor running in real mode; Pe = 1, processor running in protection mode. PG controls the paging management mechanism. Pg = 0. Disable the paging management mechanism. In this case, linear addresses generated by the segmented management mechanism are directly used as physical addresses. Pg = 1. Enable the paging management mechanism, in this case, linear addresses are converted to physical addresses by pagination management. Details about the paging management mechanism are described in the following article. The following table lists how processors work by using the PE and PG bit options. Since the page sharding mechanism can be enabled only in the protected mode, although the two bits are 0 and 1 can have four combinations, only three combinations are effective. Pe = 0 and PG = 1 are invalid combinations. Therefore, loading the Cr0 register with a PG value of 1 and PE value of 0 will cause a general protection exception. Note that the system enables or disables the paging mechanism when the PG bit is changed, therefore, PG bit can be changed only when the code of the executed program and at least some data have the same address in the linear address space and physical address space.

PG and PE Location and location Processor Operating Mode	PG	PE	How processors work
	0	0	Real Mode
	0	1	Protection Mode: Disable the paging mechanism.
	1	0	Invalid combination
	1	1	Protection Mode: Enable Paging

2. bit 1-4 in the coprocessor control bit control register Cr0 is marked as MP (arithmetic bit), EM (analog bit), and TS (Task Switching bit) respectively) and et (extended type bit), which control the operations of the floating point coprocessor. When the processor is reset, The et bit is initialized to indicate the type of the digital coprocessor in the system. If 80387 coprocessor exists in the system, et location 1; if 80287 coprocessor exists in the system or no coprocessor exists, et bit is cleared to 0. The EM bit controls whether the execution of floating point commands is simulated by software or by hardware. When em = 0, the hardware controls the floating point instruction to be transmitted to the coprocessor; when Em = 1, the floating point instruction is simulated by software. The ts bit is used to speed up task switching. It is achieved by performing coprocessor switching when necessary. Each time a task is switched, the processor sets ts to 1. When Ts = 1, the floating point command will generate a device unavailability (DNA) exception. The MP bit controls whether a DNA exception occurs when the wait command is Ts = 1. When MP = 1 and TS = 1, wait generates an exception. When MP = 0, the wait command ignores the TS condition and does not generate an exception. 3. Cr2 AND Cr 3 control registers (CR2 AND Cr 3) are used by the paging management mechanism. Cr2 is used to report error information when a page exception occurs. When a page exception occurs, the processor stores the linear address that causes the page exception in cr2. The page exception handler in the operating system can check the content of Cr2 to find out which page in the linear address space caused this exception. The first physical address of the page Directory table to be saved. Because the directory is page-aligned, only the 20-bit high is valid, and the 12-bit low is retained. When a new value is added to the product, the 12-bit lower value must be 0, but the 12-bit lower value is ignored. When you reset the value of with the mov command, the content in the paging mechanism's high-speed buffer is invalid. This method can be used before the paging mechanism is enabled, that is, before the PG position 1, pre-refresh the cache of the paging mechanism. The 33rd register can be loaded even when the PG or PE bit of the Cr0 register is 0. For example, in real mode, it can be set to make paging mechanism initialization. During task switching, the value of the new job and the value of the original job must be changed.
So that the processor does not refresh the paging high-speed cache, so that the task can be quickly executed when the table is shared. <2> the Global Descriptor Table gdt, Local Descriptor Table LDT, and Interrupt Descriptor Table idt in the system address register are all important special segments in the protection mode, they contain important tables for the segment mechanism. To facilitate fast locating of these segments, the processor uses some special registers to save the base address and segment boundary of these segments. These special registers are called system address registers. 1. The Global Descriptor Table register GDTR is shown in the table at the beginning of this article. GDTR is 48 bits in length, with 32 bits as the base address and 16 bits as the boundary. Since gdt cannot have descriptors defined within the gdt itself, the processor uses GDTR to provide a pseudo descriptor for the special system segment of gdt. GDTR specifies gdt, as shown in.

The segment boundary in GDTR is in bytes. Because the segment selection has only 13 characters as the descriptor index, and each descriptor is 8 bytes long, the 16-bit limit is sufficient. Typically, the segment boundary for a descriptor table containing N descriptors is set to 8 * N-1. The structure type can be used to define pseudo descriptors as follows:

    PDESC STRUC    LIMIT DW 0    BASE  DD 0    PDESC ENDS

2. Local Descriptor Table register ldtr specifies the Local Descriptor Table LDT used by the current task. As shown in the table at the beginning of this article, ldtr is similar to a segment register, which consists of a 16-bit register visible to the programmer and a high-speed buffer register invisible to the programmer. In fact, the Local Descriptor Table LDT of each task acts as a special segment of the system and is described by a descriptor. The LDT descriptor is stored in gdt. During initialization or task switching, the descriptor Selection Sub of the descriptor corresponding to the task LDT is loaded into ldtr, and the processor loads the Selection Sub of the visible part of ldtr, obtain the corresponding descriptor from gdt, and save the base address, boundaries, and attributes of LDT to ldtr.
See the high-speed buffer register. Then, LDT access can be checked based on the information stored in the high-speed buffer register. The ldtr register contains the Selection Sub-of the LDT of the current task. Therefore, the selection child loaded to ldtr must determine a system segment descriptor with the LDT type located in gdt, that is, the Ti bit in the selection child must be 0, the Type field in the descriptor must be LDT. You can use an empty Selection Sub-load ldtr, which indicates that the current task does not have LDT. In this case, all the selection child loaded into the segment register must indicate the descriptor in gdt, that is, the segment involved in the current task is described by the descriptor in gdt. If you load another selection sub with a Ti bit of 1 into the segment register, an exception will occur. 3. Interrupt Descriptor Table register idtr points to the Interrupt Descriptor Table IDT. As shown in the table at the beginning of this article, idtr is 48 characters long. The 32-bit base address specifies the base address of IDT, and the 16-bit limit specifies the segment limit of IDT. Because 80386 only supports 256 interruptions/exceptions, the maximum length of the IDT table is 2 K and the segment limit in bytes is 7 FFH. Idtr indicates that IDT is the same as GDTR indicates gdt. 4. Task status segment register tr task status segment register tr contains the descriptor that specifies the task status segment of the current task to select Sub, thus specifying the status segment of the current task. The format of the task status segment is described in the following article. As shown in the table at the beginning of this article, TR also contains two parts: programmer-visible and invisible. When you attach a task status segment to the tr visible part, the processor automatically saves the segment base address and other information in the descriptor of the selected sub-index to the invisible high speed.
Buffer register. After that, you can quickly and conveniently access the current task status segment. The selection subitem loaded to tr cannot be blank. the descriptor must be indexed in gdt, And the descriptor type must be TSS.

80386 The following table lists the control registers and system address registers. They are used to control the way of work, control the implementation of the segmentation management mechanism and paging management mechanism.

Control System Register	CRX	Bit31	BIT30-BIT12	BIT11-BIT5	Bit4	Bit3	Bit2	Bit1	Bit0
	Cr0	PG	0000000000000000		Et	TS	Em	MP	PE
	CR1	Retained
	CR2	Page Fault linear address
	303.	Page Directory physical page number		000000000000

	BIT47-BIT16	BIT15-BIT0
Global Descriptor Table register GDTR	Base Address	Boundary
Interrupt Descriptor Table register idtr	Base Address	Boundary

BIT15-BIT0 Local Descriptor Table register ldtr Select Sub- Task status segment register tr Select Sub-

BIT31-BIT0 BIT31-BIT0 BIT11-BIT0 Base Address Boundary Attribute Base Address Boundary Attribute

<1> as shown in the preceding table, 80386 has four 32-bit control registers named Cr0, CR1, CR2, and C3. However, CR1 is retained for future development of processors. CR1 cannot be used in 80386; otherwise, invalid command operation exceptions may occur. Cr0 includes the control bit that shows how the processor works, including the control bit that enables and disables the paging management mechanism, and the control bit that controls the operation of the floating point coprocessor. Cr2 AND Cr 3 are used by the paging management mechanism. In Cr0, digits 5-30 and bits 0 to bits 11 are reserved bits. These bits cannot be random values and must be 0. The low 16-bit control register Cr0 is equivalent to 80286 of the machine status word MSW. 1. the bit 0 in the protection control bit control register Cr0 is marked with PE, and the bit 31 is marked with PG. These two bits control segment and paging management mechanisms, so they are called protection control bit. PE controls the segment management mechanism. Pe = 0, processor running in real mode; Pe = 1, processor running in protection mode. PG controls the paging management mechanism. Pg = 0. Disable the paging management mechanism. In this case, linear addresses generated by the segmented management mechanism are directly used as physical addresses. Pg = 1. Enable the paging management mechanism, in this case, linear addresses are converted to physical addresses by pagination management. Details about the paging management mechanism are described in the following article. The following table lists how processors work by using the PE and PG bit options. Since the page sharding mechanism can be enabled only in the protected mode, although the two bits are 0 and 1 can have four combinations, only three combinations are effective. Pe = 0 and PG = 1 are invalid combinations. Therefore, loading the Cr0 register with a PG value of 1 and PE value of 0 will cause a general protection exception. Note that the system enables or disables the paging mechanism when the PG bit is changed, therefore, PG bit can be changed only when the code of the executed program and at least some data have the same address in the linear address space and physical address space.

PG and PE Location and location Processor Operating Mode	PG	PE	How processors work
	0	0	Real Mode
	0	1	Protection Mode: Disable the paging mechanism.
	1	0	Invalid combination
	1	1	Protection Mode: Enable Paging

2. bit 1-4 in the coprocessor control bit control register Cr0 is marked as MP (arithmetic bit), EM (analog bit), and TS (Task Switching bit) respectively) and et (extended type bit), which control the operations of the floating point coprocessor. When the processor is reset, The et bit is initialized to indicate the type of the digital coprocessor in the system. If 80387 coprocessor exists in the system, et location 1; if 80287 coprocessor exists in the system or no coprocessor exists, et bit is cleared to 0. The EM bit controls whether the execution of floating point commands is simulated by software or by hardware. When em = 0, the hardware controls the floating point instruction to be transmitted to the coprocessor; when Em = 1, the floating point instruction is simulated by software. The ts bit is used to speed up task switching. It is achieved by performing coprocessor switching when necessary. Each time a task is switched, the processor sets ts to 1. When Ts = 1, the floating point command will generate a device unavailability (DNA) exception. The MP bit controls whether a DNA exception occurs when the wait command is Ts = 1. When MP = 1 and TS = 1, wait generates an exception. When MP = 0, the wait command ignores the TS condition and does not generate an exception. 3. Cr2 AND Cr 3 control registers (CR2 AND Cr 3) are used by the paging management mechanism. Cr2 is used to report error information when a page exception occurs. When a page exception occurs, the processor stores the linear address that causes the page exception in cr2. The page exception handler in the operating system can check the content of Cr2 to find out which page in the linear address space caused this exception. The first physical address of the page Directory table to be saved. Because the directory is page-aligned, only the 20-bit high is valid, and the 12-bit low is retained. When a new value is added to the product, the 12-bit lower value must be 0, but the 12-bit lower value is ignored. When you reset the value of with the mov command, the content in the paging mechanism's high-speed buffer is invalid. This method can be used before the paging mechanism is enabled, that is, before the PG position 1, pre-refresh the cache of the paging mechanism. The 33rd register can be loaded even when the PG or PE bit of the Cr0 register is 0. For example, in real mode, it can be set to make paging mechanism initialization. During task switching, the value of the new job and the value of the original job must be changed.
So that the processor does not refresh the paging high-speed cache, so that the task can be quickly executed when the table is shared. <2> the Global Descriptor Table gdt, Local Descriptor Table LDT, and Interrupt Descriptor Table idt in the system address register are all important special segments in the protection mode, they contain important tables for the segment mechanism. To facilitate fast locating of these segments, the processor uses some special registers to save the base address and segment boundary of these segments. These special registers are called system address registers. 1. The Global Descriptor Table register GDTR is shown in the table at the beginning of this article. GDTR is 48 bits in length, with 32 bits as the base address and 16 bits as the boundary. Since gdt cannot have descriptors defined within the gdt itself, the processor uses GDTR to provide a pseudo descriptor for the special system segment of gdt. GDTR specifies gdt, as shown in.

The segment boundary in GDTR is in bytes. Because the segment selection has only 13 characters as the descriptor index, and each descriptor is 8 bytes long, the 16-bit limit is sufficient. Typically, the segment boundary for a descriptor table containing N descriptors is set to 8 * N-1. The structure type can be used to define pseudo descriptors as follows:

    PDESC STRUC    LIMIT DW 0    BASE  DD 0    PDESC ENDS

2. Local Descriptor Table register ldtr specifies the Local Descriptor Table LDT used by the current task. As shown in the table at the beginning of this article, ldtr is similar to a segment register, which consists of a 16-bit register visible to the programmer and a high-speed buffer register invisible to the programmer. In fact, the Local Descriptor Table LDT of each task acts as a special segment of the system and is described by a descriptor. The LDT descriptor is stored in gdt. During initialization or task switching, the descriptor Selection Sub of the descriptor corresponding to the task LDT is loaded into ldtr, and the processor loads the Selection Sub of the visible part of ldtr, obtain the corresponding descriptor from gdt, and save the base address, boundaries, and attributes of LDT to ldtr.
See the high-speed buffer register. Then, LDT access can be checked based on the information stored in the high-speed buffer register. The ldtr register contains the Selection Sub-of the LDT of the current task. Therefore, the selection child loaded to ldtr must determine a system segment descriptor with the LDT type located in gdt, that is, the Ti bit in the selection child must be 0, the Type field in the descriptor must be LDT. You can use an empty Selection Sub-load ldtr, which indicates that the current task does not have LDT. In this case, all the selection child loaded into the segment register must indicate the descriptor in gdt, that is, the segment involved in the current task is described by the descriptor in gdt. If you load another selection sub with a Ti bit of 1 into the segment register, an exception will occur. 3. Interrupt Descriptor Table register idtr points to the Interrupt Descriptor Table IDT. As shown in the table at the beginning of this article, idtr is 48 characters long. The 32-bit base address specifies the base address of IDT, and the 16-bit limit specifies the segment limit of IDT. Because 80386 only supports 256 interruptions/exceptions, the maximum length of the IDT table is 2 K and the segment limit in bytes is 7 FFH. Idtr indicates that IDT is the same as GDTR indicates gdt. 4. Task status segment register tr task status segment register tr contains the descriptor that specifies the task status segment of the current task to select Sub, thus specifying the status segment of the current task. The format of the task status segment is described in the following article. As shown in the table at the beginning of this article, TR also contains two parts: programmer-visible and invisible. When you attach a task status segment to the tr visible part, the processor automatically saves the segment base address and other information in the descriptor of the selected sub-index to the invisible high speed.
Buffer register. After that, you can quickly and conveniently access the current task status segment. The selection subitem loaded to tr cannot be blank. the descriptor must be indexed in gdt, And the descriptor type must be TSS.