Control Register
(The control registers (Cr0, CR1, CR2, and so on) are used to control and determine the operating mode of the processor and the features of the currently executed tasks .)
As shown in the preceding table, 80386 has four 32-bit control registers named Cr0, CR1, CR2, and C3. However, CR1 is retained for future development of processors. CR1 cannot be used in 80386; otherwise, invalid command operation exceptions may occur. Cr0 includes the control bit indicating the processing method of the processor, including the control bit that enables and disables the paging management mechanism, and the control bit that controls the floating point coprocessor operation. Cr2 AND Cr 3 are used by the paging management mechanism. In Cr0, digits 5-30 and bits 0 to bits 11 are reserved bits. These bits cannot be random values and must be 0.
The low 16-bit control register Cr0 is equivalent to 80286 of the machine status word MSW.
1. Protection Control bit in Cr0
The bit 0 in the control register Cr0 is marked with PE, and the bit 31 is marked with PG. These two bits control the operations of the segmentation and paging management mechanisms, so they are called protection control bits. PE controls the segment management mechanism. Pe = 0, processor running in real mode; Pe = 1, processor running in protection mode. PG controls the paging management mechanism. Pg = 0. Disable the paging management mechanism. In this case, linear addresses generated by the segmented management mechanism are directly used as physical addresses. Pg = 1. Enable the paging management mechanism, in this case, linear addresses are converted to physical addresses by pagination management. We can see that if you want to enable the paging mechanism, you must set the PE and PG flags.
The following table lists how processors work by using the PE and PG bit options. Since the paging mechanism can be enabled only in the protection mode, although the two bits are 0 and 1 can have four combinations, only three combinations are effective. Pe = 0 and PG = 1 are invalid combinations. Therefore, loading the Cr0 register with a PG value of 1 and PE value of 0 will cause a general protection exception. Note that the system enables or disables the paging mechanism when the PG bit is changed, therefore, the PG bit can be changed only when the code of the executed program and at least some data have the same address in the linear address space and physical address space.
2. coprocessor control bit
The bit 1-4 in the control register Cr0 is marked as MP (arithmetic bit) and EM (analog bit, used to select the protocol used to communicate with the coprocessor, respectively, that is, it indicates whether 80386 or 80286 coprocessor is used in the system), TS (Task Switching bit) and ET (extended type bit), they control the operation of floating point coprocessor.
When the processor is reset, The et bit is initialized to indicate the type of the digital coprocessor in the system. If 80387 coprocessor exists in the system, et location 1; if 80287 coprocessor exists in the system or no coprocessor exists, et bit is cleared to 0. The EM bit controls whether the execution of floating point commands is simulated by software or by hardware. When em = 0, the hardware controls the floating point instruction to be transmitted to the coprocessor; when Em = 1, the floating point instruction is simulated by software. The ts bit is used to speed up task switching. It is achieved by performing coprocessor switching when necessary. Each time a task is switched, the processor sets ts to 1. When Ts = 1, the floating point command will generate a device unavailability (DNA) exception. The MP bit controls whether a DNA exception occurs when the wait command is Ts = 1. When MP = 1 and TS = 1, wait generates an exception. When MP = 0, the wait command ignores the TS condition and does not generate an exception.
When the system is powered on, the processor is reset to PE = 0, Pg = 0 (that is, the real mode status ), to allow Boot Code to initialize these registers and data structures before the segmentation and paging mechanisms are enabled. This type of register can be used only in real mode.
3. Cr2 AND Cr 3
The control registers Cr2 AND Cr 3 are used by the paging management mechanism.
Cr2 is used to report error information when a page exception occurs. When a page exception occurs, the processor stores the linear address that causes the page exception in cr2. The page exception handler in the operating system can check the content of Cr2 to find out which page in the linear address space caused this exception.
It is called pdbr because it is used to save the physical address of the page Directory Table Page. Because directories are page-aligned, only 20-bit high is valid, and 12-bit low is retained for more advanced processors. When a new value is added to the clause, the value of 12 lower digits must be 0, but the value of 12 lower digits is ignored. When you reset the value of with the mov command, the content in the paging mechanism's high-speed buffer is invalid. This method can be used before the paging mechanism is enabled, that is, before the PG position 1, pre-refresh the cache of the paging mechanism. The Audit audit. During task switching, the value of the new task must be changed. However, if the value of the new task is the same as that of the original task, the processor does not refresh the paging high-speed cache, in this way, the task can be quickly executed when the page table is shared. |
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In addition to Cr0, there are four control registers. CR1 is not used (or is secretly used, but not described in this document). Cr2 stores a page failure address when the processor is in protected mode, the address of the storage page Directory of Cr 3, which is implemented by the Pentium series (including later versions of version 486) processor. The transactions it processes include, for example, when Virtual 8086 mode is enabled. |
