Cortex A8 Processor Start profiling a boot code BL0

The Cortex A8 is a processor based on the ARMV7 architecture, with a frequency of up to 1GHz. The processor based on CortexA8 has Samsung's s5pc100, S5pv210,ti's OMAP3530, and the A10 of all Chi. I have an idea that U-boot's 2-stage code is independent. The first phase of code is called hardware-related BL1, and the second-stage code is called hardware-independent BL2. There is just a piece of s5pc100 board on hand, it introduces the s5pc100 and verifies the starting process. I divided the start-up process into 3 stages BL0, BL1, BL2. BL0 is cured in the internal ROM on the implementation of a small program, I wrote the boot code, used to boot u-boot called BL2, the u-boot of the second stage code for the boot kernel is called BL2. This is my understanding, in the next I will analyze BL0, BL1, BL2, and implement BL1 code boot U-BOOT,BL2 move to the kernel.

First, what is BL0

The BL0 (1st boot loader) is a small piece of program that is cured on the internal ROM. The BL0 loads the second boot program from the system-specified external memory (NAND, SD/MMC, Onenand, and USB) BL1 to internal RAM, while the BL1 is securely inspected. The startup process is as follows:

Second, what did BL0 do?

S5PC100 chip manual See 2.2FUNCTIONAL SEQUENCE, translated into Chinese as follows

1. Initialize the PLL and clock to set it to a fixed value;
2. Initialize stack and heap area;
3. Initialize the command cache controller;
4. Load the BL1 from the external starting device;
5. If the starting security mechanism is turned on, check the BL1 data integrity;
6. If the check passes, jump to the 0x34010 address to run;
7. Stop if the checksum fails.

Iii. s5pc100 supported start-up mode

Depending on the configuration of om[4:0], b0[5::0] pins, different boot modes can be supported
OM[4] 0: Normal mode 1: Test mode
OM[3] 0: Start from internal ROM first 1: Boot from NOR flash
OM[2:1]00: Second boot from NAND flash 01: Second boot from one NAND10: Second boot from MMC/SD card 11: Second boot from nor Flash
OM[0] APLL/MPLL Input Selection
B0[5] 0: Second start up by om[2:1] OK 1: Second boot from USB (when Om[2:1] is 00 o'clock from NAND flash boot)
B0[4] 0:ECC encryption 1::ECC not encrypted
B0[3] 0
B0[2] Address cycle selection
B0[1:0] Block Size selection 00:small block page 10:large block (page 2048) 11:dlarge block (page 4096)

Note If starting from SD/MMC, the BL0 will sd/mmc the last 9KB data to the 0x34000, and if starting from Onenand and NAND, BL0 will load the starting 16KB data to run at the 0x34000.

Reference article: http://www.tuxi.com.cn/6-132-1327758.html